Register 7:
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 270
Register 8:
UART Control (UARTCTL), offset 0x030 ......................................................................... 272
Register 9:
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 274
Register 10:
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 276
Register 11:
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 278
Register 12:
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 279
Register 13:
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 280
Register 14:
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 282
Register 15:
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 283
Register 16:
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 284
Register 17:
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 285
Register 18:
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 286
Register 19:
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 287
Register 20:
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 288
Register 21:
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 289
Register 22:
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 290
Register 23:
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 291
Register 24:
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 292
Register 25:
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 293
Synchronous Serial Interface (SSI) ............................................................................................ 294
Register 1:
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 306
Register 2:
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 308
Register 3:
SSI Data (SSIDR), offset 0x008 ...................................................................................... 310
Register 4:
SSI Status (SSISR), offset 0x00C ................................................................................... 311
Register 5:
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 313
Register 6:
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 314
Register 7:
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 316
Register 8:
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 317
Register 9:
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 318
Register 10:
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 319
Register 11:
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 320
Register 12:
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 321
Register 13:
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 322
Register 14:
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 323
Register 15:
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 324
Register 16:
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 325
Register 17:
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 326
Register 18:
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 327
Register 19:
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 328
Register 20:
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 329
Register 21:
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 330
Inter-Integrated Circuit (I
2C) Interface ........................................................................................ 331
Register 1:
I
2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 345
Register 2:
I
2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 346
Register 3:
I
2C Master Data (I2CMDR), offset 0x008 ......................................................................... 350
Register 4:
I
2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 351
Register 5:
I
2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 352
Register 6:
I
2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 353
15
September 02, 2007
Preliminary
LM3S8730 Microcontroller