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LM3S6916-IQN25-B0 데이터시트(PDF) 5 Page - List of Unclassifed Manufacturers

부품명 LM3S6916-IQN25-B0
상세설명  Microcontroller
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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LM3S6916-IQN25-B0 데이터시트(HTML) 5 Page - List of Unclassifed Manufacturers

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10
General-Purpose Timers ................................................................................................. 197
10.1
Block Diagram ........................................................................................................................ 197
10.2
Functional Description ............................................................................................................. 198
10.2.1 GPTM Reset Conditions .......................................................................................................... 199
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 199
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 200
10.3
Initialization and Configuration ................................................................................................. 204
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 204
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 205
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 205
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 206
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 206
10.3.6 16-Bit PWM Mode ................................................................................................................... 207
10.4
Register Map .......................................................................................................................... 207
10.5
Register Descriptions .............................................................................................................. 208
11
Watchdog Timer ............................................................................................................... 233
11.1
Block Diagram ........................................................................................................................ 233
11.2
Functional Description ............................................................................................................. 233
11.3
Initialization and Configuration ................................................................................................. 234
11.4
Register Map .......................................................................................................................... 234
11.5
Register Descriptions .............................................................................................................. 235
12
Analog-to-Digital Converter (ADC) ................................................................................. 256
12.1
Block Diagram ........................................................................................................................ 257
12.2
Functional Description ............................................................................................................. 257
12.2.1 Sample Sequencers ................................................................................................................ 257
12.2.2 Module Control ........................................................................................................................ 258
12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 259
12.2.4 Analog-to-Digital Converter ...................................................................................................... 259
12.2.5 Test Modes ............................................................................................................................. 259
12.3
Initialization and Configuration ................................................................................................. 259
12.3.1 Module Initialization ................................................................................................................. 259
12.3.2 Sample Sequencer Configuration ............................................................................................. 259
12.4
Register Map .......................................................................................................................... 260
12.5
Register Descriptions .............................................................................................................. 261
13
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 288
13.1
Block Diagram ........................................................................................................................ 289
13.2
Functional Description ............................................................................................................. 289
13.2.1 Transmit/Receive Logic ........................................................................................................... 289
13.2.2 Baud-Rate Generation ............................................................................................................. 290
13.2.3 Data Transmission .................................................................................................................. 291
13.2.4 Serial IR (SIR) ......................................................................................................................... 291
13.2.5 FIFO Operation ....................................................................................................................... 292
13.2.6 Interrupts ................................................................................................................................ 292
13.2.7 Loopback Operation ................................................................................................................ 293
13.2.8 IrDA SIR block ........................................................................................................................ 293
13.3
Initialization and Configuration ................................................................................................. 293
13.4
Register Map .......................................................................................................................... 294
13.5
Register Descriptions .............................................................................................................. 295
5
November 30, 2007
Preliminary
LM3S6916 Microcontroller


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