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STA015B 데이터시트(PDF) 7 Page - STMicroelectronics |
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STA015B 데이터시트(HTML) 7 Page - STMicroelectronics |
7 / 44 page VDD 100nF 1 2 VDD 100nF 14 13 VSS VDD 100nF 16 15 VDD 100nF 23 22 VSS VSS VSS 17 18 28 26 RESET 24 TESTEN OUT_CLK/DATA_REQ VDD PVSS PVDD 100nF 4.7 µF 4.7 µF PVDD PVSS VSS 10K 1K 4.7nF PVSS 470pF 19 20 21 8 7 6 5 12 11 10 9 4 3 XTO XTI SCR_INT 27 LRCK_ADC BIT_EN 25 SDI_ADC SCKR SDI OCLK LRCKT SCKT SDO SCL SDA D00AU1143 Figure 3. Test Circuit (refer to SO28 package) IOL IOH CL VREF VDD OUTPUT D98AU967 Figure 4. Test Load Circuit Output IOL IOH CL VREF SDA 1mA 100pF 3.6V Other Outputs 100 µA 100 µA 100pF 1.5V Test Load 2. FUNCTIONAL DESCRIPTION 2.1 - Clock Signal The STA015 input clock is derivated from an ex- ternal source or from a industry standard crystal oscillator, generating input frequencies of 10, 14.31818 or 14.7456 MHz. Other frequencies may be supported upon re- quest to STMicroelectronics. Each frequency is supported by downloading a specific configura- tion file, provided by STM XTI is an input Pad with specific levels. Symbol Parameter Test Condition Min. Typ. Max. Unit VIL Low Level Input Voltage VDD-1.8 V VIH High Level Input Voltage VDD-0.8 V CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD = 3V TTL min high level = 2.0V while XTI min high level = 2.2V) STA015-STA015B-STA015T 7/44 |
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