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STB24NF10 데이터시트(PDF) 1 Page - STMicroelectronics |
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1 / 6 page STB24NF10 N - CHANNEL 100V - 0.07 Ω - 24A TO-263 LOW GATE CHARGE STripFET ™ POWER MOSFET PRELIMINARY DATA s TYPICAL RDS(on) = 0.07 Ω s EXCEPTIONAL dv/dt CAPABILITY s 100% AVALANCHE TESTED s SURFACE-MOUNTING D 2PAK (TO-263) POWER PACKAGE IN TAPE & REEL (SUFFIX ”T4”) DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency, high-frequency isolated DC-DC converters for Telecom and Computer applications. It is also intended for any applications with low gate drive requirements. APPLICATIONS s HIGH-EFFICIENCY DC-DC CONVERTERS s UPS AND MOTOR CONTROL ® INTERNAL SCHEMATIC DIAGRAM April 2000 ABSOLUTE MAXIMUM RATINGS Symb ol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 100 V VDGR Drain- gate Voltage (RGS =20 k Ω) 100 V VGS G ate-source Volt age ± 20 V ID Drain Current (continuous) at Tc =25 oC24 A ID Drain Current (continuous) at Tc = 100 oC15 A IDM( •) Drain Current (pulsed) 96 A Ptot T otal Dissipation at Tc =25 oC80 W Derating Factor 0.53 W / oC dv/ dt(1 ) Peak Diode Recovery voltage slope 9 V/ns EAS (2) Single Pulse Avalanche Energy 75 mJ Tstg Storage Temperature -65 to 175 oC Tj Max. Operating Junction Temperature 175 oC ( •) Pulse width limited by safe operating area ( 2) starting Tj =25 oC, I D =24A , VDD = 50V (1) ISD ≤ 24 A, di/dt ≤ 300A/µs, V DD ≤ V (BR)DSS,Tj ≤ T JMA TYPE VDSS RDS(on ) ID STB24NF10 100 V < 0.077 Ω 24 A 1 3 D 2PAK TO-263 (Suffix ”T4”) 1/6 |
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