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전자부품 데이터시트 검색엔진 |
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Q67121-C1061 데이터시트(PDF) 5 Page - Siemens Semiconductor Group |
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Q67121-C1061 데이터시트(HTML) 5 Page - Siemens Semiconductor Group |
5 / 43 page ![]() Semiconductor Group 4 1996 Intermediate Version C161 Pin Definitions and Functions Symbol Pin Number Input Output Function XTAL1 XTAL2 2 3 I O XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. P3.2 – P3.13 5 – 16 I/O I/O Port 3 is a 12-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 3 pins also serve for alternate functions: 5 I P3.2 CAPIN GPT2 Register CAPREL Capture Input This function is only available on the C161O. 6 7 8 9 10 O I I I I P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture These functions are only available on the C161K and the C161O. 11 12 13 14 15 16 I/O I/O O I/O O O I/O P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE Ext. Memory High Byte Enable Signal, WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P4.0 – P4.5 17-20, 23, 24 17 ... 24 I/O I/O O ... O Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line ... ... ... P4.5 A21 Most Significant Segment Addr. Line RD 25 O External Memory Read Strobe. RD is activated for every external instruction or data read access. |
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