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TDA758013TR 데이터시트(PDF) 11 Page - STMicroelectronics |
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TDA758013TR 데이터시트(HTML) 11 Page - STMicroelectronics |
11 / 39 page TDA7580 Block diagram and electrical specifications 11/39 21 GND G Digital core power ground 22 VDD P Digital core power supply 1.8V 23 IQSYNC B High speed synchronous serial interface (HS3I) clock if HS3I master mode, else DSP1 GPIO or DSP1 debug port clock (DBOUT1) DSP1 GPIO0 5V tolerant. With internal pull-up, on at reset Input 24 IQCH1 B High speed synchronous serial interface (HS3I) channel 1 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port request (DBRQ1) DSP1 GPIO1 5V tolerant. With internal pull-up, on at reset [PP] Input 25 IQCH2 B High speed synchronous serial interface (HS3I) channel 2 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port data In (DBIN1) DSP1 GPIO2 5V tolerant. With internal pull-down, on at reset [PP] Input 26 IQCH3 B High speed synchronous serial interface (HS3I) channel 3 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port data out (DBCK1) DSP1 GPIO3 5V tolerant With internal pull-down, on at reset [PP] Input 27 VDDH P 3.3V IO ring power supply (HS3I, I2C/SPI, RDS, INT) 28 GNDH G 3.3V IO ring power ground (HS3I, I2C/SPI, RDS, INT) 29 RDS_INT B RDS interrupt to external main microprocessor in case of traffic information DSP1 GPIO4. 5V tolerant, open drain With internal pull-up, on at reset [OD] Input 30 RDS_CS B RDS chip select. When RESETN rising, If RDS_CS 0, the RDS’s SPI is selected; else RDS’s I2C DSP1 GPIO5. 5V tolerant. With internal pull-up, on at reset [PP] Input 31 INT I DSP0 external interrupt 5V tolerant. With internal pull-up, on at reset 32 ADDR_SD B IFS chip master (Low) or slave (High) mode selection, latched in upon RESETN release. It selects the LSB of the I2C addresses. Station detector output DSP0 GPIO2 5V tolerant With internal pull-down, on at reset [PP] Input 33 RESETN I Chip hardware reset, active low 5V tolerant With internal pull-up 34 VDD P Digital power supply 1.8V 35 GND G Digital power ground 36 TESTN I Test enable pin, active low With internal pull-up Table 5. Pin description (continued) N° Name Type Description Notes After Reset |
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