전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

LC5768MC-5F256I 데이터시트(PDF) 15 Page - Lattice Semiconductor

부품명 LC5768MC-5F256I
상세설명  3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family
Download  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  LATTICE [Lattice Semiconductor]
홈페이지  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LC5768MC-5F256I 데이터시트(HTML) 15 Page - Lattice Semiconductor

Back Button LC5768MC-5F256I Datasheet HTML 11Page - Lattice Semiconductor LC5768MC-5F256I Datasheet HTML 12Page - Lattice Semiconductor LC5768MC-5F256I Datasheet HTML 13Page - Lattice Semiconductor LC5768MC-5F256I Datasheet HTML 14Page - Lattice Semiconductor LC5768MC-5F256I Datasheet HTML 15Page - Lattice Semiconductor LC5768MC-5F256I Datasheet HTML 16Page - Lattice Semiconductor LC5768MC-5F256I Datasheet HTML 17Page - Lattice Semiconductor LC5768MC-5F256I Datasheet HTML 18Page - Lattice Semiconductor LC5768MC-5F256I Datasheet HTML 19Page - Lattice Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 92 page
background image
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
15
Clock Distribution
The ispXPLD 5000MX family has four dedicated clock input pins: GCLK0-GCLK3. GLCK0 and GCLK3 can be
routed through a PLL circuit or routed directly to the internal clock nets. The internal clock nets (CLK0-CLK3) are
directly related to the dedicated clock pins (see Secondary Clock Divider exception when using the sysCLOCK cir-
cuit). These feed the registers in the MFBs. Note at each register there is the option of inverting the clock if
required. Figure 14 shows the clock distribution network.
Figure 14. Clock Distribution Network
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset and feedback
signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener-
ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are de-
skewed either at the board level or the device level.
The ispXPLD 5000MX devices provide two PLL circuits. PLL0 receives its clock inputs from GCLK 0 and provides
outputs to CLK 0 (CLK 1 when using the secondary clock). PLL1 operates with signals from GCLK 3 and CLK 3
(CLK 2 when using the secondary clock). The optional outputs CLK_OUT can be routed to an I/O pin. The optional
PLL_LOCK output is routed into the GRP. The optional input PLL_RST can be routed either from the GRP or
directly from an I/O pin. The optional PLL_FBK into can be routed directly from a pin. Figure 15 shows the ispXPLD
5000MX PLL block diagram. Figure 16 shows the connection of optional inputs and outputs.
sysCLOCK PLLs
Global Clock Routing
Clock Net
PLL0
CLK_OUT0
SEC_OUT0
VREF0
CLK0
CLK1
GCLK0
GCLK1
I/O/CLK_OUT0
Clock Net
Clock Net
PLL1
CLK_OUT1
SEC_OUT1
CLK3
CLK2
GCLK3
GCLK2
I/O/CLK_OUT1
Clock Net
To Macrocells
To Macrocells
To Macrocells
To Macrocells
VREF1
VREF3
VREF2


유사한 부품 번호 - LC5768MC-5F256I

제조업체부품명데이터시트상세설명
logo
Lattice Semiconductor
LC5768MC-5F256C LATTICE-LC5768MC-5F256C Datasheet
427Kb / 92P
   3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family
More results

유사한 설명 - LC5768MC-5F256I

제조업체부품명데이터시트상세설명
logo
Lattice Semiconductor
LC5256MC LATTICE-LC5256MC Datasheet
427Kb / 92P
   3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family
LC4512Z LATTICE-LC4512Z Datasheet
851Kb / 91P
   3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4032C LATTICE-LC4032C Datasheet
483Kb / 74P
   3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
ISPMACH4000V LATTICE-ISPMACH4000V Datasheet
451Kb / 99P
   3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
logo
Altera Corporation
EPM7064LI44-15 ALTERA-EPM7064LI44-15 Datasheet
1Mb / 66P
   Programmable Logic Device Family
EPM3512AQC208-10N ALTERA-EPM3512AQC208-10N Datasheet
715Kb / 46P
   Programmable Logic Device Family
EPM7064STI44-7N ALTERA-EPM7064STI44-7N Datasheet
1Mb / 66P
   Programmable Logic Device Family
EPF8452AQC160-3 ALTERA-EPF8452AQC160-3 Datasheet
957Kb / 62P
   Programmable Logic Device Family
EPM7064STI44-7 ALTERA-EPM7064STI44-7 Datasheet
1Mb / 66P
   Programmable Logic Device Family
EPM7032LC44-15 ALTERA-EPM7032LC44-15 Datasheet
1Mb / 66P
   Programmable Logic Device Family
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com