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LC4064V-5TN48C 데이터시트(PDF) 4 Page - Lattice Semiconductor |
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4 / 99 page Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 4 Figure 2. Generic Logic Block AND Array The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con- nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being fed to the macrocells. Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0. There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND Array. 36 Inputs from GRP To GRP To Product Term Output Enable Sharing 1+OE Clock Generator 1+OE 1+OE 1+OE 1+OE 1+OE 1+OE 1+OE |
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