LC871HC8A/96A

No.A1189-4/27

Interrupts

• 40 sources, 10 vector addresses

1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of

the level equal to or lower than the current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level

takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector

address takes precedence.

No.

Vector Address

Level

Interrupt Source

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L/INT4/UHC bus active/remote control signal receive

4

0001BH

H or L

INT3/INT5/base timer

5

00023H

H or L

T0H/INT6/UHC device connected/UHC disconnected/UHC resume

6

0002BH

H or L

T1L/T1H/INT7/SIO9/AIF start

7

00033H

H or L

SIO0/UART1 receive

8

0003BH

H or L

SIO1/SIO4/UART1 transmit/end of AIF

9

00043H

H or L

ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC STALL

10

0004BH

H or L

Port 0/PWM0/PWM1/T4/T5/UHC-SOF/DMCOPY

• Priority levels X > H > L

• Of interrupts of the same level, the one with the smallest vector address takes precedence.

Subroutine Stack Levels: 8192 levels maximum (The stack is allocated in RAM.)

High-speed Multiplication/Division Instructions

• 16 bits × 8 bits

(5 tCYC execution time)

• 24 bits × 16 bits

(12 tCYC execution time)

• 16 bits ÷ 8 bits

(8 tCYC execution time)

• 24 bits ÷ 16 bits

(12 tCYC execution time)

Oscillation and PLL Circuits

• RC oscillation circuit (internal):

For system clock

• CF oscillation circuit:

For system clock

• Crystal oscillation circuit:

For system clock, time-of-day clock

• PLL circuit (internal):

For USB interface (see Fig.5)), audio interface (see Fig. 6)

Standby Function

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.

1) Oscillation is not halted automatically.

2) There are three ways of resetting the HALT mode.

(1) Setting the reset pin to the lower level.

(2) Reset generated by watchdog timer

(3) Interrupt generation

• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.

1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation.

2) There are five ways of resetting the HOLD mode.

(1) Setting the reset pin to the lower level.

(2) Reset generated by watchdog timer

(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level

(4) Having an interrupt source established at port 0

(5) Having an bus active interrupt source established in the USB host controll circuit

Continued on next page.