DDR Clock Oscillator

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5

Detailed Description

The DS4266 consists of a fundamental-mode crystal

and synthesizer IC packaged in a 5mm x 3.2mm x

1.49mm, 10-pin LCCC ceramic package. The device

produces a frequency output of 266.00MHz. Two differ-

ential output types are available: LVDS and LVPECL.

The device output can be enabled or disabled through

the OE signal input. When the OE signal is low, LVPECL

the LVDS outputs are a logical 1. See Figures 2 and 3

for LVDS and LVPECL output timing diagrams.

Additional Information

For more available frequencies in the DS4-XO family,

X1

X2

THREE-

STATE

PHASE

DET

FILTER

LC-VCO

/n

OUTSELN

/m

OUTDRV

GND

OE

OUTP

OUTN

DS4266

Figure 1. Functional Diagram

OE

OUTP

OUTN

Figure 2. LVDS Output Timing Diagram When OE Is Enabled

and Disabled

OE

OUTP

PECL_BIAS

PECL_BIAS

PECL_BIAS

PECL_BIAS

OUTN

Figure 3. LVPECL Output Timing Diagram When OE Is Enabled

and Disabled