74LVT573_4

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 — 15 September 2008

4 of 16

NXP Semiconductors

74LVT573

3.3 V octal D-type transparent latch; (3-state)

5.2 Pin description

6.

Functional description

6.1 Function table

[1]

H = HIGH voltage level;

L = LOW voltage level;

↓ = HIGH-to-LOW latch enable transition;

h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition;

l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition;

Z = high-impedance OFF-state;

NC = no change;

X = don’t care.

7.

Limiting values

Table 2.

Pin description

Symbol

Pin

Description

OE

1

output enable input (active LOW)

D0 to D7

2, 3, 4, 5, 6, 7, 8, 9

data input

GND

10

ground (0 V)

LE

11

latch enable (active HIGH)

Q0 to Q7

19, 18, 17, 16, 15, 14, 13, 12

data output

20

supply voltage

Table 3.

Function table [1]

Operating mode

Control OE

Control LE

Input Dn

Internal register Output Qn

Load and read register

enable

LH

LLL

HHH

Latch and read register

L

↓

lL

L

hH

H

Hold

L

L

X

NC

NC

Disable outputs

H

X

X

NC

Z

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

−0.5

+4.6

V

input voltage

[1]

−0.5

+7.0

V

output voltage

output in OFF-state or HIGH-state

[1]

−0.5

+7.0

V

input clamping current

-

−50

mA

output clamping current

-

−50

mA

output current

output in LOW-state

-

128

mA

output in HIGH-state

-

−64

mA