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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ISP1583 데이터시트(PDF) 37 Page - NXP Semiconductors |
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ISP1583 데이터시트(HTML) 37 Page - NXP Semiconductors |
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37 / 100 page  ISP1583_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 22 September 2008 36 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller 9.2.4.1 Session Request Protocol (SRP) The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing, followed by VBUS pulsing. The A-device can detect either data-line pulsing or VBUS pulsing. The ISP1583 can initiate the B-device SRP by performing the following steps: 1. Set the OTG bit to start SRP. 2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG register. 3. Start data-line pulsing: set bit DP of the OTG register to logic 1. 4. Wait for 5 ms to 10 ms. 5. Stop data-line pulsing: set bit DP of the OTG register to logic 0. 6. Start VBUS pulsing: set bit VP of the OTG register to logic 1. 7. Wait for 10 ms to 20 ms. 8. Stop VBUS pulsing: set bit VP of the OTG register to logic 0. 9. Discharge VBUS for about 30 ms: optional by using bit DISCV of the OTG register. 10. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG cleared. 11. Once bit BSESSVALID is detected, turn on the SOFTCT bit to start normal bus enumeration. The B-device must complete both data-line pulsing and VBUS pulsing within 100 ms. Remark: When disabling OTG, data-line pulsing bit DP and VBUS pulsing bit VP must be cleared by writing logic 0. 9.2.5 Interrupt Enable register (address: 14h) This register enables or disables individual interrupt sources. The interrupt for each endpoint can individually be controlled using the associated bits IEPnRX or IEPnTX, here n represents the endpoint number. All interrupts can be globally disabled using bit GLINTENA in the Mode register (see Table 24). An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the USB bus. The interrupt generation depends on Debug mode settings of bit fields CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0] in the Interrupt Configuration register. All data IN transactions use the Transmit buffers (TX), which are handled by bits DDBGMODIN[1:0]. All data OUT transactions go through the Receive buffers (RX), which are handled by bits DDBGMODOUT[1:0]. Transactions on control endpoint 0 (IN, OUT and SETUP) are handled by bits CDBGMOD[1:0]. Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up and high-speed status) can also be individually controlled. A bus reset disables all enabled interrupts, except bit IEBRST (bus reset), which remains logic 1. The Interrupt Enable register consists of 4 bytes. The bit allocation is given in Table 32. |
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