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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ISP1583 데이터시트(PDF) 47 Page - NXP Semiconductors |
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ISP1583 데이터시트(HTML) 47 Page - NXP Semiconductors |
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47 / 100 page  ISP1583_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 22 September 2008 46 of 99 NXP Semiconductors ISP1583 Hi-Speed USB peripheral controller In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer counter can still be programmed, it will not have any effect on the DMA transfer. The DMA transfer will start once the DMA command is issued. Any of the following three ways will terminate this DMA transfer: • Detecting an external EOT • Detecting an internal EOT (short packet on an OUT token) • Issuing a GDMA stop command There are three interrupts programmable to differentiate the method of DMA termination: bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt Reason register (see Table 74). MDMA (master) read/write (opcode = 06h/07h) — Generic DMA master mode. Depending on the MODE[1:0] bits set in the DMA Configuration register, the DACK, DIOR or DIOW signal strobes data. These signals are driven by the ISP1583. In master mode, BURSTCOUNTER[12:0] in the DMA Burst Counter register, DIS_XFER_CNT in the DMA Configuration register and the external EOT signal are not applicable. The DMA transfer counter is always enabled and bit DMA_XFER_OK is set to 1 once the counter reaches 0. MDMA read/write (opcode = 06h/07h) — Multi-word DMA mode for IDE transfers. The specification of this mode can be obtained from Ref. 4 “AT Attachment with Packet Interface Extension (ATA/ATAPI-4), ANSI INCITS 317-1998 (R2003)”. DIOR and DIOW are used as data strobes, while DREQ and DACK serve as handshake signals. Table 49. Control bits for Generic DMA transfers Control bits Description Reference GDMA read/write (opcode = 00h/01h) MDMA (master) read/write (opcode = 06h/07h) DMA Configuration register ATA_MODE set to logic 0 (non-ATA transfer) set to logic 1 (ATA transfer) Table 56 DMA_MODE[1:0] - determines MDMA timing for DIOR and DIOW strobes DIS_XFER_CNT disables use of DMA transfer counter disables use of DMA transfer counter MODE[1:0] determines active read/write data strobe signals determines active data strobe(s) WIDTH selects DMA bus width: 8 or 16 bits selects DMA bus width: 8 or 16 bits |
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