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STFLWARP11PL 데이터시트(PDF) 1 Page - STMicroelectronics |
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1 / 19 page W.A.R.P. 1.1 WEIGHT ASSOCIATIVE RULE PROCESSOR ADVANCED DATA High Speed Rules Processing Antecedent Membership Functions with any Shape Up to 256 Rules (4 Antecedents,1 Consequent) Up to 16 Input Configurable Variables Up to 16 Membership Functions for an Input Variable Up to 16 Output Variables Up to 128 Membership Functions for all Consequents MAX-DOT Inference Method Defuzzification on chip Software Tools and Emulators Availability 100-pin CPGA100 Ceramic Package 84-lead Plastic Leaded Chip Carrier package GENERAL DESCRIPTION W.A.R.P. is a VLSI Fuzzy Logic controller whose architecture arises from the need of realizing an integrated structure with high inferencing perform- ances and flexibility. To get those results a modular architecture based on a set of parallel memory blocks has been implemented. In order to obtainhigh performances W.A.R.P. uses different data representations during the various phases of the computational cycle, so that it is always operating on the optimal data repre- sentation. A vectorial characterization has been adopted for the Antecedent Membership Func- tions. W.A.R.P. exploits a SGS-THOMSON pat- ented strategy to store the Antecedent Membership May 1996 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice. 8 I0-I7 A0-A9 10 O0-O9 FIN 3 CHM OFL 4 OCNT0-OCNT3 STB EP NP PRS T MCLK VS S VDD W.A.R.P. 1.1 10 EPA0-EPA2 S YNC Figure 1. Logic Diagram Number of Inputs Configurable [1..8] Standard Rule Format 4 Antecedents, 1 Consequent [or subsets] Rules Number Max 256 Rules in the 4 Antecedent, 1 Consequent format Antecedent’s MFs Number Configurable [up to 16 for an input variable] Consequent’s MFs Number Max 256 for all outputs variables Input Data Resolution 8 bit Output Data Resolution 8 bit Table 1. W.A.R.P. Configuration Settings CPGA 100 PLCC84 1/19 |
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