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STFLWARP11PL 데이터시트(PDF) 4 Page - STMicroelectronics |
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STFLWARP11PL 데이터시트(HTML) 4 Page - STMicroelectronics |
4 / 19 page Functions in dedicated memories in order to reduce the computational time. Therefore a great amount of W.A.R.P. processing is based on a look-up table approach rather than on on-line calculation. Those Membership Functions (MFs), each one portrayed by a configurable resolution of 26 or 27 elements, are stored in four internal RAMs (1Kbyte each). The consequent MFs, due to the different modelling, are loaded in a single RAM by storing for each MF its area and its barycentre. This is due to the adoption of the Center of Gravity defuzzifica- tion method. The downloading phase allows the setting of the device, in terms of I/O number, universes of dis- course and MF shapes. During this phase W.A.R.P. prepares its internal memories for the on-line elaboration phase and loads the microcode in its program memory. This microcode, which drives the on-line phase, is generated by the Compiler (see W.A.R.P.-SDT User Manual) according to the adopted configuration. The possible configurations are shown in table 1. During the on-line phase (up to 40MHz working frequency), W.A.R.P. processes the input data and produces its outputs according to the configuration loaded in the downloading phase. W.A.R.P. is conceived to work together with tradi- Name Pins Type Function VDD - Power Supply VSS - Ground A0-A9 I/O Memory Address Bus I0-I7 I Data Input Bus PRST I Preset FIN I First Input Signal OFL I Off-Line/On-Line Switch CHM I Charge Mode Switch TE I Testing (it must be connected to VSS) MTE I Testing (it must be connected to VSS) MCLK I Clock (up to 40 MHz) EPA0-EPA2 * O EPROM Address Bus O0-O9 O Defuzzified Output OCNT0-OCNT3 O Output Counter STB O Strobe (Output Ready Signal) EP O End Process NP O New Process OTST O Testing (it must be connected to VSS) OMTS O Testing (it must be connected to VSS) SYNC O External Synchronization Table 4. Pin Description tional microcontrollers which shall perform normal control tasks while W.A.R.P. will be indipendently responsible for all the fuzzy related computing. W.A.R.P. is manufactured using the high perform- ance, reliable HCMOS4T (O.7 µm) SGS-THOM- SON Microelectronics process. PIN DESCRIPTION VDD,VSS: Power is supplied to W.A.R.P. using these pins. VDD is the power connection and VSS is the ground connection; multi-connections are nec- essary. A0-A9: When the CHM pin is low they accept as input the addresses for the internal memory bus. In the off-line mode they are used to address W.A.R.P. memories where the microprogram and data of antecedent and consequentmembership functions must be loaded. Each A0-A9 word is composed by assembling the data contained in the memory support related to .cs and .add files (see W.A.R.P.-SDT User Manual). In particular, couples of data respectively coming from .cs and .add files are joined to form a single A0-A9 word in the following way: * Pins not used in W.A.R.P. 1.0 4/19 W.A.R.P.1.1 |
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