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STC5230-I 데이터시트(PDF) 10 Page - Connor-Winfield Corporation |
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STC5230-I 데이터시트(HTML) 10 Page - Connor-Winfield Corporation |
10 / 48 page Data Sheet #: TM102 Page 10 of 48 Rev: P01 Date: August 22, 2007 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5230 Synchronous Clock for SETS Data Sheet Preliminary 0x41 T4_Long_Term_Accu_History 31-0 R Long term Accumulated History for T4 relative to MCLK 0x45 T4_Short_Term_Accu_History 31-0 R Short term Accumulated History for T4 relative to MCLK 0x49 T4_User_Accu_History 31-0 R/W User Holdover data for T4 relative to MCLK 0x4d T4_History_Ramp 6-0 R/W Bits 6-4, Long term history accumulation bandwidth: 9.7, 4.9, 2.4, 1.2, 0.61, 0.03 mHz Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62, 0.31 Hz Bits 1-0, Ramp control: none, 1, 1.5, 2 ppm/s 0x4e T4_Priority_Table 47-0 R/W REF1-12 selection priority for automatic mode, 4 bits/reference 0x54 T4_PLL_Status 7-0 R OOP, LOL, LOS, Sync, HHR, AHR, SAP 0x55 T4_Accu_Flush 0-0 W 0: Flush/reset the long-term history, 1: Flush/reset both the long- term and the device holdover history 0x56 CLK0_Sel 1-0 R/W 155.52/125 MHz clock select or disable for CLK0 0x57 CLK1_Sel 2-0 R/W 19.44/38.88/51.84/77.76/25/50/125 MHz or disable select for CLK1 0x58 CLK2_Sel 2-0 R/W 19.44/38.88/51.84/77.76/25/50/125 MHz or disable select for CLK2 0x59 CLK3_Sel 5-0 R/W 8kHz output 50% duty cycle or pulse width selection for CLK3 0x5a CLK4_Sel 5-0 R/W 2kHz output 50% duty cycle or pulse width selection for CLK4 0x5b CLK5_Sel 1-0 R/W DS3/E3 select for CLK5 0x5c CLK6_Sel 3-0 R/W DS1 x n / E1 x n selector for CLK6 0x5d CLK7_Sel 1-0 R/W DS1/E1 selector for CLK7 0x5e Intr_Event 9-0 R/W Interrupt event 0x60 Intr_Enable 9-0 R/W Interrupt enable 0x62 T0_MS_PHE 19-0 R Round-trip phase delay of T0’s cross-couple data links 0x65 CLK8_Sel 1-0 R/W 155.52/125 MHz clock select or disable for CLK8 Extra Registers if LM is configured as BUS_LOAD_MODE 0x70 Bus_Loader_Status 2-0 R Status of the bus loader of the configuration data 0x71 Bus_Loader_Data 7-0 W Data port of the bus loader of the configuration data 0x72 Bus_Loader_Counter 13-0 R Data counter of the bus loader of the configuration data Extra Registers if LM is configured as EEP_LOAD_MODE 0x70 EEP_Loader_Checksum 0-0 R Checksum status of the EEPROM loader of the configuration data 0x71 EEP_Controller_Mode 7, 0 R/W Mode of the EEPROM controller 0x72 EEP_Controller_Cmd 1-0 W Command to the EEPROM controller 0x73 EEP_Controller_Page 7-0 W Page number to the EEPROM controller 0x74 EEP_Controller_Data 7-0 R/W Data port of the EEPROM controller Table 4: Register Map Addr Reg Name Bits Type Description |
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