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TC500 데이터시트(PDF) 11 Page - TelCom Semiconductor, Inc |
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TC500 데이터시트(HTML) 11 Page - TelCom Semiconductor, Inc |
11 / 17 page 3-29 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514 Figure 6. Noise S N TH Low REF S N TH Normal V REF S N TH High 30 µV V REF SLOPE (S) = NTH = Noise Threshold VREF RINT CINT Figure 7. Overshoot INTEGRATOR OUTPUT COMPARATOR OUTPUT COMP INTEGRATE PHASE DEINTEGRATE PHASE INTEGRATOR ZERO PHASE ZERO CROSSING OVERSHOOT Figure 8 shows the overall timing for a typical system in which a TC5xx is interfaced to a microcontroller. The microcontroller drives the A, B inputs with I/O lines and monitors the comparator output, CMPTR, using an I/O line or dedicated timer-capture control pin. It may be necessary to monitor the state of the CMPTR output in addition to having it control a timer directly for the Reference Deintegra- tion phase. (This is further explained below.) The timing diagram in Figure 8 is not to scale as the timing in a real system depends on many system parameters and component value selections. There are four critical timing events (as shown in Figure 8): sampling the input polarity; capturing the deintegration time; minimizing over- shoot and properly executing the Integrator Output Zero phase. Auto-Zero Phase The length of this phase is usually set to be equal to the Input Signal Integration time. This decision is virtually arbi- trary since the magnitudes of the various system errors are not known. Setting the Auto-Zero time equal to the Input Integrate time should be more than adequate to null out system errors. The system may remain in this phase indefi- nitely, i.e., Auto-Zero is the appropriate idle state for a TC5xx device. Input Signal Integrate Phase The length of this phase is constant from one conversion to the next and depends on system parameters and compo- nent value selections. The calculation of tINT is shown elsewhere in this data sheet. At some point near the end of this phase, the microcontroller should sample CMPTR to determine the input signal polarity. This value is, in effect, the Sign Bit for the overall conversion result. Optimally, CMPTR should be sampled just before this phase is termi- nated by changing AB from 10 to 11. The consideration here ) DESIGN CONSIDERATIONS Noise The threshold noise (NTH) is the algebraic sum of the integrator noise and the comparator noise. This value is typically 30 µV. Figure 6 shows how the value of the refer- ence voltage can affect the final count. Such errors can be reduced by increased integration times, in the same way that 50/60Hz noise is rejected. The signal-to-noise ratio is related to the integration time (tINT) and the integration time constant (RINT) (CINT) as follows: S/N (dB) = 20 Log VIN • tINT 30 x 10–6 (RINT) • (CINT) System Timing To obtain maximum performance from the TC5xx, the overshoot at the end of the Deintegration phase must be minimized. Also, the Auto Zero phase must be terminated as soon as the comparator output returns high. (See timing diagram, Figure 8). ( |
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