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RT3PE3000L-1FG484B ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Actel Corporation

๋ถ€ํ’ˆ๋ช… RT3PE3000L-1FG484B
์ƒ์„ธ๋‚ด์šฉ  Radiation-Tolerant ProASIC3 Low-Power Space- Flight Flash FPGAs
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RT3PE3000L-1FG484B ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Actel Corporation

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Radiation-Tolerant ProASIC3 Device Family Overview
1- 2
A d vance v0.1
technology, an RT ProASIC3 device is able to retain device SRAM and logic while dynamic power is
reduced to a minimum, without the need to stop clock or power supplies. Combining these
features provides a low-power, feature-rich, and high-performance solution.
Security
Nonvolatile, flash-based RT ProASIC3 devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. RT ProASIC3 devices incorporate FlashLock, which
provides a unique combination of reprogrammability and design security without external
overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
RT ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure
programmed intellectual property and configuration data. In addition, all FlashROM data in RT
ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192)
bit block cipher encryption standard. AES was adopted by the National Institute of Standards and
Technology (NIST) in 2000 and replaces the 1977 DES standard. RT ProASIC3 devices have a built-in
AES decryption engine and a flash-based AES key that make them the most comprehensive
programmable logic device security solution available today. RT ProASIC3 devices with AES-based
security allow for secure, remote field updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP
thieves. The contents of a programmed device cannot be read back, although secure design
verification is possible.
Security, built into the FPGA fabric, is an inherent component of the RT ProASIC3 family. The flash
cells are located beneath seven metal layers, and many device design and layout techniques have
been used to make invasive attacks extremely difficult. The RT ProASIC3 family, with FlashLock and
AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP possible. An RT ProASIC3 device provides
the most impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,
the configuration data is an inherent part of the FPGA structure, and no external configuration
data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based RT
ProASIC3 FPGAs do not require system configuration components such as EEPROMs or
microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB
area, and increases security and system reliability.
Live at Power-Up
Actel flash-based RT ProASIC3 devices support Level 0 of the LAPU classification standard. This
feature helps in system component initialization, execution of critical tasks before the processor
wakes up, setup and configuration of memory blocks, clock generation, and bus activity
management. The LAPU feature of flash-based RT ProASIC3 devices greatly simplifies total system
design and reduces total system cost, often eliminating the need for CPLDs and clock generation
PLLs. In addition, glitches and brownouts in system power will not corrupt the
device's flash
configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system
power is restored. This enables the reduction or complete removal of the configuration PROM,
expensive voltage monitor, brownout detection, and clock generator devices from the PCB design.
Flash-based RT ProASIC3 devices simplify total system design and reduce cost and design risk while
increasing system reliability and improving system initialization time.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based RT ProASIC3 devices allow all functionality to be live at power-up;
no external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property cannot be compromised or copied.
Secure ISP can be performed using the industry-standard AES algorithm. The RT ProASIC3 family
device architecture mitigates the need for ASIC migration at higher volumes. This makes the RT
ProASIC3 family a cost-effective ASIC replacement.


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