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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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A3P1000-1FGG144T 데이터시트(PDF) 72 Page - Actel Corporation |
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A3P1000-1FGG144T 데이터시트(HTML) 72 Page - Actel Corporation |
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72 / 136 page  Automotive ProASIC3 DC and Switching Characteristics 2- 60 v1.0 Table 2-97 • Output Enable Register Propagation Delays Automotive-Case Conditions: TJ = 115°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.53 0.62 ns tOESUD Data Setup Time for the Output Enable Register 0.37 0.44 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.52 0.61 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.79 0.93 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.79 0.93 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.27 0.31 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.27 0.31 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.25 0.30 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.25 0.30 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.41 0.48 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values. |
유사한 부품 번호 - A3P1000-1FGG144T |
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유사한 설명 - A3P1000-1FGG144T |
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