74AC11074

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCAS499A – DECEMBER 1986 – REVISED APRIL 1996

1

POST OFFICE BOX 655303

Minimize High-Speed Switching Noise

CMOS) 1-

µm Process

125

°C

Small-Outline (D) and Thin Shrink

Small-Outline (PW) Packages, and

Standard Plastic 300-mil DIPs (N)

description

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)

or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR

are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the

outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is

not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may

be changed without affecting the levels at the outputs.

The 74AC11074 is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUT

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

LX

XL

H

L

LX

X

H†

H†

H

H

°

HH

L

H

H

°

LL

H

H

H

L

X

Q0

Q0

† This configuration is nonstable; that is, it does not

persist when PRE or CLR returns to its inactive

(high) level.

Copyright

© 1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

D, N, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1PRE

1Q

1Q

GND

2Q

2Q

2PRE

1CLK

1D

1CLR

2CLR

2D

2CLK