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TC4222CG-PBF 데이터시트(PDF) 9 Page - Linear Technology |
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TC4222CG-PBF 데이터시트(HTML) 9 Page - Linear Technology |
9 / 32 page LTC4222 9 4222f PIN FUNCTIONS ADIN: ADC Input. A voltage between 0 and 1.28V applied to this pin is measured by the on-board ADC. Tie to ground if unused. ADR0, ADR1, ADR2: Serial Bus Address Inputs. Tying these pins to ground, open, or INTVCC configures one of 27 possible addresses. See Table 1 in Applications Information. ALERT: Fault Alert Output. Open drain logic output that is pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by setting the corre- sponding bit in the ALERT register as shown in Table 4. See Applications Information. Tie to ground if unused. CONFIG: Configuration Input. Configures the part to control the two channels together or independently. When CONFIG is tied to GND both channels start up at the same time. A fault, EN or ON turn-off command on either channel will shut down both channels. When CONFIG is tied to INTVCC, either channel can start up independently. A fault, EN or ON turn-off command will result in the associated chan- nel turning off, while the other channel remains on. If one channel is commanded to turn on while another channel is in the turn-on sequence, the 4222 waits until the first channel has finished its turn-on sequence before turning on the second channel. EN1, EN2: Enable Input. Ground this pin to indicate a board is present and enable the N-channel MOSFET to turn-on. When this pin is high, the MOSFET is not allowed to turn on. An internal 10μA current source pulls up this pin. Transitions on this pin are recorded in the FAULT register. A high-to-low transition activates the logic to read the state of the ON pin and clear faults. See Applications Information. EXPOSED PAD: (Pin 33, QFN Package) Exposed Pad. May be left open or connected to device ground. FB1, FB2: Foldback Current Limit and Power-Good Input. A resistive divider from the output is tied to this pin. When the voltage at this pin drops below 1.235V, power is not considered good. The power bad condition may result in the GPIO pin pulling low or going high impedance depending on the configuration of CONTROL register bits 6 and 7. Also a power bad fault is logged when the FB pin is low, the LTC4222 has finished the startup cycle and the GATE pin is high. See Applications Information. The startup current limit folds back from 50mV sense voltage to 16.6mV as the FB voltage drops from 0.8V to 0.2V. Foldback is not active once the part leaves startup and the current limit is increased to 150mV. GATE1, GATE2: Gate Drive for External N-Channel MOSFET. An internal 12μA current source charges the gate of the MOSFET. No compensation capacitor is required on the GATE pin, but a resistor and capacitor network from this pin to ground may be used to set the turn-on output voltage slew rate. During turn-off there is a 1mA pull-down cur- rent. During a short circuit or under-voltage lockout (VDD or INTVCC), a 450mA pull-down current source between GATE and SOURCE is activated. GND: Device Ground. GPIO1, GPIO2: General Purpose Input/Output. Open drain logic output or logic input. Defaults to an output set to pull low to indicate power is not good. Configure according to Table 3. INTVCC: Low Voltage Supply Decoupling Output. Connect a 0.1μF capacitor from this pin to ground. ON: (QFN Package) On Control Input. Formed by internally tying the ON1 and ON2 lines together. ON1, ON2: (SSOP Package) On Control Inputs. A rising edge turns on the external N-channel FET and a falling edge turns it off. This pin also configures the state of the FET ON register bit (and hence the external FET) at power up. For example, if the ON pin is tied high, then the FET ON bit (Control bit 3 in Table 3) goes high 100ms after power-up. Likewise if the ON pin is tied low then the channel remains off after power-up until the FET ON bit is set high using the I2C bus. A high-to-low transition on this pin clears the fault register for the related channel. The two ON pins are tied together internally on the QFN package. OV1, OV2: Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 1.235V, an overvoltage fault is detected and the GATE turns off. Tie to GND if unused. |
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