전자부품 데이터시트 검색엔진 |
|
CD74HCT166E 데이터시트(PDF) 1 Page - Texas Instruments |
|
|
CD74HCT166E 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 13 page 1 Data sheet acquired from Harris Semiconductor SCHS157C Features • Buffered Inputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) Pinout CD54HC166, CD54HCT166 (CERDIP) CD74HC166, CD74HCT166 (PDIP, SOIC) TOP VIEW Description The ’HC166 and ’HCT166 8-bit shift register is fabricated with silicon gate CMOS technology. It possesses the low power consumption of standard CMOS integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky device. The ’HCT166 is functionally and pin compatible with the standard ’LS166. The 166 is an 8-bit shift register that has fully synchronous serial or parallel data entry selected by an active LOW Parallel Enable (PE) input. When the PE is LOW one setup time before the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into the internal bit position Q0 from Serial Data Input (DS), and the remaining bits are shifted one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. For expansion of the register in parallel to serial converters, the Q7 output is con- nected to the DS input of the succeeding stage. The clock input is a gated OR structure which allows one input to be used as an active LOW Clock Enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of CE input should only take place while the CP is HIGH for predictable operation. A LOW on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a LOW state. Ordering Information 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 DS D0 D1 D2 D3 CE GND CP VCC D7 Q7 D6 D5 D4 MR PE PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC166F3A -55 to 125 16 Ld CERDIP CD54HCT166F3A -55 to 125 16 Ld CERDIP CD74HC166E -55 to 125 16 Ld PDIP CD74HC166M -55 to 125 16 Ld SOIC CD74HC166MT -55 to 125 16 Ld SOIC CD74HC166M96 -55 to 125 16 Ld SOIC CD74HCT166E -55 to 125 16 Ld PDIP CD74HCT166M -55 to 125 16 Ld SOIC CD74HCT166MT -55 to 125 16 Ld SOIC CD74HCT166M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. February 1998 - Revised October 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register [ /Title (CD74 HC166 , CD74 HCT16 6) /Sub- ject (High Speed CMOS Logic 8-Bit Paral- lel- In/Seri |
유사한 부품 번호 - CD74HCT166E |
|
유사한 설명 - CD74HCT166E |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |