CDC318A

1-LINE TO 18-LINE CLOCK DRIVER

SCAS614 – SEPTEMBER 1998

7

POST OFFICE BOX 655303

switching characteristics over recommended operating conditions

PARAMETER

FROM

TO

TEST CONDITIONS

MIN

MAX

UNIT

A

Y

1.2

4.5

ns

tPLH

Low-to-high level propagation delay time

SCLOCK

↓

SDATA

valid

VCC = 3.3 V ±0.165 V,

See Figure 3

2

µs

tPLH

Low-to-high level propagation delay time

SDATA

↑

Y

VCC = 3.3 V ±0.165 V,

See Figure 3

150

ns

A

Y

1.2

4.5

ns

tPHL

High-to-low level propagation delay time

SCLOCK

↓

SDATA

valid

VCC = 3.3 V ±0.165 V,

See Figure 3

2

µs

tPHL

High-to-low level propagation delay time

SDATA

↑

Y

VCC = 3.3 V ±0.165 V,

See Figure 3

150

ns

tPZH

Enable time to the high level

OE

Y

1

7

ns

tPZL

Enable time to the low level

OE

Y

1

7

ns

tPHZ

Disable time from the high level

OE

Y

1

7

ns

tPLZ

Disable time from the low level

OE

Y

1

7

ns

tsk(o)

Skew time

A

Y

250

ps

tsk(p)

Skew time

A

Y

500

ps

tsk(pr)

Skew time

A

Y

1

ns

tr

Rise time

Y

0.5

2.2

ns

t

Rise time (see Note 5 and

SDATA

CL = 10 pF

6

ns

tr

(

Figure 3)

SDATA

CL = 400 pF

950

ns

tf

Fall time

Y

0.5

2.3

ns

tf

Fall time (see Note 5 and

SDATA

CL = 10 pF

20

ns

tf

(

Figure 3)

SDATA

CL = 400 pF

250

ns

NOTE 5: This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protection.