SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

6

POST OFFICE BOX 1443

Terminal Functions

PIN

DESCRIPTION

NAME

TYPE†

DESCRIPTION

ADDRESS AND DATA BUSES

A15 (MSB)

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0 (LSB)

I/O/Z

Parallel address bus. Multiplexed to address external data, program memory, or I/O. A0 – A15 are in the

high-impedance state in hold mode and when OFF is active (low). These signals are used as inputs for external DMA

access of the on-chip single-access RAM. They become inputs while HOLDA is active (low) if BR is driven low

externally.

D15 (MSB)

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 (LSB)

I/O/Z

Parallel data bus. Multiplexed to transfer data between the core CPU and external data, program memory, or I / O

devices. D0 – D15 are in the high-impedance state when not outputting data, when RS or HOLD is asserted, or when

OFF is active (low). These signals also are used in external DMA access of the on-chip single-access RAM.

MEMORY CONTROL SIGNALS

DS

PS

IS

O/Z

Data, program, and I/O space select signals. Always high unless asserted for communicating to a particular external

space. DS, PS, and IS are in the high-impedance state in hold mode or when OFF is active (low).

READY

I

Data ready input. Indicates that an external device is prepared for the bus transaction to be completed. If the device

is not ready (READY is low), the processor waits one cycle and checks READY again. READY also indicates a bus

grant to an external device after a BR (bus request) signal.

R/W

I/O/Z

Read / write. R / W indicates transfer direction during communication to an external device and is normally in read

mode (high) unless asserted for performing a write operation. R / W is in the high-impedance state in hold mode or

when OFF is active (low). Used in external DMA access of the 9K RAM cell, this signal indicates the direction of the

data bus for DMA reads (high) and writes (low) when HOLDA and IAQ are active (low).

STRB

I/O/Z

Strobe. Always high unless asserted to indicate an external bus cycle, STRB is in the high-impedance state in the

hold mode or when OFF is active (low). Used in external DMA access of the on-chip single-access RAM and while

HOLDA and IAQ are active (low), STRB is used to select the memory access.

RD

O/Z

Read select. RD indicates an active external read cycle and can connect directly to the output enable (OE) of external

devices. This signal is active on all external program, data, and I/O reads. RD is in the high-impedance state in hold

mode or when OFF is active (low).

† I = input, O = output, Z = high-impedance

NOTE: All input pins that are unused should be connected to VDD or an external pullup resistor. The BR pin has an internal pullup for performing

DMA to the on-chip RAM. For emulation, TRST has an internal pulldown, and TMS, TCK, and TDI have internal pullups. EMU0 and EMU1

require external pullups to support emulation.