전자부품 데이터시트 검색엔진 |
|
SMJ320C50GFAM66 데이터시트(PDF) 6 Page - Texas Instruments |
|
|
SMJ320C50GFAM66 데이터시트(HTML) 6 Page - Texas Instruments |
6 / 31 page SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR SGUS020 – JUNE 1996 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Terminal Functions PIN DESCRIPTION NAME TYPE† DESCRIPTION ADDRESS AND DATA BUSES A15 (MSB) A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) I/O/Z Parallel address bus. Multiplexed to address external data, program memory, or I/O. A0 – A15 are in the high-impedance state in hold mode and when OFF is active (low). These signals are used as inputs for external DMA access of the on-chip single-access RAM. They become inputs while HOLDA is active (low) if BR is driven low externally. D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) I/O/Z Parallel data bus. Multiplexed to transfer data between the core CPU and external data, program memory, or I / O devices. D0 – D15 are in the high-impedance state when not outputting data, when RS or HOLD is asserted, or when OFF is active (low). These signals also are used in external DMA access of the on-chip single-access RAM. MEMORY CONTROL SIGNALS DS PS IS O/Z Data, program, and I/O space select signals. Always high unless asserted for communicating to a particular external space. DS, PS, and IS are in the high-impedance state in hold mode or when OFF is active (low). READY I Data ready input. Indicates that an external device is prepared for the bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. READY also indicates a bus grant to an external device after a BR (bus request) signal. R/W I/O/Z Read / write. R / W indicates transfer direction during communication to an external device and is normally in read mode (high) unless asserted for performing a write operation. R / W is in the high-impedance state in hold mode or when OFF is active (low). Used in external DMA access of the 9K RAM cell, this signal indicates the direction of the data bus for DMA reads (high) and writes (low) when HOLDA and IAQ are active (low). STRB I/O/Z Strobe. Always high unless asserted to indicate an external bus cycle, STRB is in the high-impedance state in the hold mode or when OFF is active (low). Used in external DMA access of the on-chip single-access RAM and while HOLDA and IAQ are active (low), STRB is used to select the memory access. RD O/Z Read select. RD indicates an active external read cycle and can connect directly to the output enable (OE) of external devices. This signal is active on all external program, data, and I/O reads. RD is in the high-impedance state in hold mode or when OFF is active (low). † I = input, O = output, Z = high-impedance NOTE: All input pins that are unused should be connected to VDD or an external pullup resistor. The BR pin has an internal pullup for performing DMA to the on-chip RAM. For emulation, TRST has an internal pulldown, and TMS, TCK, and TDI have internal pullups. EMU0 and EMU1 require external pullups to support emulation. |
유사한 부품 번호 - SMJ320C50GFAM66 |
|
유사한 설명 - SMJ320C50GFAM66 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |