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SN74ABT821ANT 데이터시트(PDF) 1 Page - Texas Instruments |
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SN74ABT821ANT 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 7 page SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS193E – FEBRUARY 1991 – REVISED MAY 1997 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs description These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the devices provide true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impe- dance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT821 is characterized for operation over the full military temperature range of –55 °C to 125°C. The SN74ABT821A is characterized for operation from –40 °C to 85°C. Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC- ΙΙB is a trademark of Texas Instruments Incorporated. SN54ABT821 . . . JT OR W PACKAGE SN74ABT821A . . . DB, DW, OR NT PACKAGE (TOP VIEW) SN54ABT821 . . . FK PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK 32 1 28 27 12 13 5 6 7 8 9 10 11 25 24 23 22 21 20 19 3Q 4Q 5Q NC 6Q 7Q 8Q 3D 4D 5D NC 6D 7D 8D 426 14 15 16 17 18 NC – No internal connection |
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