전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SN74ABTH182502A 데이터시트(PDF) 7 Page - Texas Instruments

Click here to check the latest version.
부품명 SN74ABTH182502A
상세설명  SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
Download  37 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

SN74ABTH182502A 데이터시트(HTML) 7 Page - Texas Instruments

Back Button SN74ABTH182502A Datasheet HTML 3Page - Texas Instruments SN74ABTH182502A Datasheet HTML 4Page - Texas Instruments SN74ABTH182502A Datasheet HTML 5Page - Texas Instruments SN74ABTH182502A Datasheet HTML 6Page - Texas Instruments SN74ABTH182502A Datasheet HTML 7Page - Texas Instruments SN74ABTH182502A Datasheet HTML 8Page - Texas Instruments SN74ABTH182502A Datasheet HTML 9Page - Texas Instruments SN74ABTH182502A Datasheet HTML 10Page - Texas Instruments SN74ABTH182502A Datasheet HTML 11Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 37 page
background image
SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A
SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected
or if a board defect causes it to be open circuited.
For the ’ABTH18502A and ’ABTH182502A, the instruction register is reset to the binary value 10000001, which
selects the IDCODE instruction. Bits 47–44 in the boundary-scan register are reset to logic 1, ensuring that
these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked,
the outputs would be at high-impedance state). Reset values of other bits in the boundary-scan register should
be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the
PSA test operation.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR
state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.


유사한 부품 번호 - SN74ABTH182502A

제조업체부품명데이터시트상세설명
logo
Texas Instruments
SN74ABTH182502A TI-SN74ABTH182502A Datasheet
802Kb / 42P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74ABTH182502A TI-SN74ABTH182502A Datasheet
832Kb / 42P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74ABTH182502APM TI-SN74ABTH182502APM Datasheet
802Kb / 42P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74ABTH182502APM TI-SN74ABTH182502APM Datasheet
832Kb / 42P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
More results

유사한 설명 - SN74ABTH182502A

제조업체부품명데이터시트상세설명
logo
Texas Instruments
SN54ABTH18502A TI-SN54ABTH18502A_08 Datasheet
832Kb / 42P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABTH18502A TI-SN54ABTH18502A_07 Datasheet
802Kb / 42P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABT18245A TI-SN54ABT18245A Datasheet
357Kb / 28P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS
SN54ABT18245A TI-SN54ABT18245A_06 Datasheet
436Kb / 32P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS
SN54ABT18245A TI-SN54ABT18245A_08 Datasheet
617Kb / 34P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS
SN54ABT18504 TI-SN54ABT18504_08 Datasheet
665Kb / 34P
[Old version datasheet]   SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABTH18504A TI-SN54ABTH18504A_08 Datasheet
763Kb / 39P
[Old version datasheet]   SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABTH18504A TI-SN54ABTH18504A Datasheet
547Kb / 35P
[Old version datasheet]   SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABT18504 TI-SN54ABT18504 Datasheet
450Kb / 30P
[Old version datasheet]   SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN54ABT18640 TI-SN54ABT18640 Datasheet
400Kb / 30P
[Old version datasheet]   SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com