MDA_ADCDS-1603.E06 Page 5 of 11

Fine Gain Adjustment

For fine gain adjustment model, contact the factory.

Output Coding

The ADCDS-1603's output coding is Straight Binary as indicated in

Table 1. The table shows the relationship between the output data

coding and the difference between the reference signal voltage and

its corresponding pixel data signal voltage.

Optimal Performance

Disturbances to the system while the A/D is undergoing a conversion

can result in degradation of performance. It is therefore recommended

that both digital and analog signals (including the Reference/Pixel data

inputs to the ADCDS) not be allowed to switch during a time window of

150ns to 300ns following the rising edge of the Start Convert command

when operating in the 0°C to 70°C temperature range, and from 140ns

to 320ns for the extended temperature range. See timing Figure 7

"A/D Critical Conversion Window."

The max conversion rate of 2.3MHz for the ADCDS-1603 is dictated by

the settling time of the input circuitry and the conversion time require-

ment of the A/D converter. Switching the analog input from Reference

to pixel data 300ns after the rising edge of Start Convert allows a suf-

ficient amount of settling time (approx. 130ns) for the pixel data input

signal to settle to the 16 bit accuracy. In the unique application where

the Reference to Pixel data signal is presented to the ADCDS-1603 prior

to the 120ns to 300ns restriction it may be possible to increase the

ADCDS-1603 conversion rate up to 3MHz.

Note: At initial power-up, the first 186 conversions should be ignored.

Table 1. Output Coding

Reference – Pixel Data

(V)

Scale

Digital Output

>+2.048

2.048

1.536

1.024

0.512

0.256

0.00003125

0

<0

>Full Scale

Full Scale -1LSB

3/4FS

1/2FS

1/4FS

1/8FS

1LSB

0

<0

1111 1111 1111 1111

1111 1111 1111 1110

11 0000 0000 0000

10 0000 0000 0000

01 0000 0000 0000

00 1000 0000 0000

00 0000 0000 0001

00 0000 0000 0000

0000 0000 0000 0000

Resultant signal from internal CDS (Input to A/D). Assumes Input Amplifier gain set properly.

See "Modes of Operation" section.

The pixel data portion of the differential signal must be more negative than its associated

.

+5VD

–5VA

34

38

5

4

3

23

22

21

20

19

18

17

16

15

14

13

12

11

10

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

27

+2.048V REFERENCE OUT

DATA VALID

ADCDS-1603

4.7μF

0.1μF

4.7μF

0.1μF

ANALOG GROUND

NON-INVERTING INPUT

INVERTING INPUT

DIRECT INPUT

+5VA

36

7, 35, 37

4.7μF

0.1μF

26

25

REF. HOLD

START CONVERT

2

6

20K

+5V

–5V

OFFSET ADJUST

External Series

Resistor

32, 33 DIGITAL GROUND

30

31

A1

A0

BIT 15

BIT 16 (LSB)

9

8

0.1μF

0.1μF

0.1μF

4.7μF

See

Figures

2a–2f

Figure 6. ADCDS-1603 Connection Diagram

ADCDS-1603

16-Bit, 2.3 Megapixels/Second

CCD Signal Processor

www.murata-ps.com