SN54ALS20A, SN54AS20, SN74ALS20A, SN74AS20

DUAL 4-INPUT POSITIVE-NAND GATES

SDAS192B – APRIL 1982 – REVISED DECEMBER 1994

Copyright

1

POST OFFICE BOX 655303

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

These devices contain two independent 4-input

positive-NAND gates. They perform the Boolean

functions Y = A

• B • C • D or Y = A + B + C + D

in positive logic.

The

SN54ALS20A

and

SN54AS20

are

characterized for operation over the full military

temperature range of – 55

°C to 125°C. The

SN74ALS20A and SN74AS20 are characterized

for operation from 0

°C to 70°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

C

D

Y

H

H

H

H

L

L

XX

X

H

X

LX

X

H

X

XL

X

H

X

X

X

L

H

logic diagram (positive logic)

&

1Y

6

2Y

8

1

1A

2

1B

4

1C

5

1D

9

2A

10

2B

12

2C

13

2D

1Y

1D

1A

1B

1C

2C

2B

2A

2D

2Y

1

2

4

5

9

10

12

13

6

8

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

SN54ALS20A, SN54AS20 ...J PACKAGE

SN74ALS20A, SN74AS20 ...D OR N PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

NC

1C

1D

1Y

GND

2D

2C

NC

2B

2A

2Y

SN54ALS20A, SN54AS20 . . . FK PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

2C

NC

NC

NC

2B

NC

NC

1C

NC

1D

NC – No internal connection

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.