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DESCRIPTION

Drvr

Conn.

0.25”

0.875”

0.625”

0.625”

1”

1”

Slot 1

Slot 2

0.625”

0.625”

1”

1”

Slot 16

Slot 8

0.25”

Conn.

Conn.

Conn.

Rcvr

Rcvr

Rcvr

t − Time − ns

10

30

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0

20

TI GTL16612A

Fairchild GTLP16612

TI GTL16612

SN54GTL16612A, SN74GTL16612A

18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS

SCES187D – JANUARY 1999 – REVISED JULY 2005

•

Bus Hold on A-Port Inputs Eliminates the

Need for External Pullup/Pulldown Resistors

•

Members of the Texas Instruments Widebus™

Family

•

Minimizes High-Speed Switching Noise

•

Universal Bus Transceiver (UBT™) Combines

D-Type Latches and D-Type Flip-Flops for

•

ESD Protection Exceeds JESD 22

Operation in Transparent, Latched, Clocked,

– 2000-V Human-Body Model (A114-A)

or Clock-Enabled Modes

– 200-V Machine Model (A115-A)

•

Translate Between GTL/GTL+ Signal Levels

– 1000-V Charged-Device Model (C101)

and LVTTL Logic Levels

•

Latch-Up Performance Exceeds 100 mA Per

•

Support Mixed-Mode (3.3-V and 5-V) Signal

JESD 78, Class II

Operation on A-Port and Control Inputs

•

Package Options Include Plastic Shrink

•

B-Port Transition Time Optimized for

Small-Outline (DL), Thin Shrink Small-Outline

Distributed Backplane Loads

(DGG), and Ceramic Flat (WD) Packages

•

xxx

Operation

The 'GTL16612A devices are 18-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL+ and

GTL+-to-LVTTL signal-level translation. They allow for transparent, latched, clocked, or clock-enabled modes of

data transfer. These devices provide a high-speed interface between cards operating at LVTTL logic levels and

backplanes operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL)

backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and

output edge control (OEC™). Improved GTL+ OEC circuits minimize bus settling time and have been designed

and tested using several backplane models.

Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is a

16-slot, 14-inch board with loaded impedance of 33

Ω. V

The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot-1 signals are

shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing

between receiver cards is reduced. The clock is independent of the data, and the system clock frequency is

limited by the backplane flight time to about 80-90 MHz. This frequency can be increased even more (30% to

40%) if the clock is generated and transmitted together with the data from the driver card (source synchronous).

Figure 1. Test Backplane Model With Output Waveform Results

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, UBT, OEC, TI are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 1999–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

On products compliant to MIL-PRF-38535, all parameters are

Instruments standard warranty. Production processing does not

tested unless otherwise noted. On all other products, production

necessarily include testing of all parameters.

processing does not necessarily include testing of all parameters.