SN54HCT125, SN74HCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS069C – NOVEMBER 1988 – REVISED MAY 1997

1

POST OFFICE BOX 655303

Lines or Buffer Memory Address Registers

Small-Outline (D) and Ceramic Flat (W)

Packages, Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J)

300-mil DIPs

description

These bus buffer gates feature independent line

drivers with 3-state outputs. Each output is

disasbled when the associated output-enable

(OE) input is high.

The SN54HCT125 is characterized for operation

over the full military temperature range of –55

°C

to 125

°C. The SN74HCT125 is characterized for

operation from –40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

OE

A

Y

L

H

H

L

LL

H

X

Z

EN

1

2

1B

4

5

2B

10

9

3B

13

12

4B

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, N, and W packages.

1Y

3

1OE

2OE

3OE

4OE

2Y

6

3Y

8

4Y

11

Copyright

© 1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54HCT125 ...J OR W PACKAGE

SN74HCT125 ...D OR N PACKAGE

(TOP VIEW)

32 1 20 19

910 11 1213

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3OE

1Y

NC

2OE

NC

2A

SN54HCT125 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y