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SN74ABT3611PQ 데이터시트(PDF) 7 Page - Texas Instruments

부품명 SN74ABT3611PQ
상세설명  64 횞 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
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SN74ABT3611PQ 데이터시트(HTML) 7 Page - Texas Instruments

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SN74ABT3611
64
× 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FIFO write/read operation (continued)
Table 2. Port-A Enable Function Table
CSA
W/RA
ENA
MBA
CLKA
A0 – A35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
In high-impedance state
FIFO write
L
H
H
H
In high-impedance state
Mail1 write
L
L
L
L
X
Active, mail2 register
None
L
L
H
L
Active, mail2 register
None
L
L
L
H
X
Active, mail2 register
None
L
L
H
H
Active, mail2 register
Mail2 read (set MBF2 high)
The port-B control signals are identical to those of port A. The state of the port-B data (B0 – B35) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0 – B35 outputs are
in the high-impedance state when either CSB or W/RB is high. The B0 – B35 outputs are active when both CSB
and W/RB are low. Data is read from the FIFO to the B0 – B35 outputs by a low-to-high transition of CLKB when
CSB is low, W/RB is low, ENB is high, MBB is high, and EF is high (see Table 3).
Table 3. Port-B Enable Function Table
CSB
W/RB
ENB
MBB
CLKB
B0 – B35 OUTPUTS
PORT FUNCTION
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
In high-impedance state
None
L
H
H
H
In high-impedance state
Mail2 write
L
L
L
L
X
Active, FIFO output register
None
L
L
H
L
Active, FIFO output register
FIFO read
L
L
L
H
X
Active, mail1 register
None
L
L
H
H
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.


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