전자부품 데이터시트 검색엔진 |
|
SN74ABT3612PCB 데이터시트(PDF) 10 Page - Texas Instruments |
|
SN74ABT3612PCB 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 31 page SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 almost-full flags (AFA, AFB) (continued) transition of the synchronizing clock after the FIFO read that reduces the number of words in memory to [64 – (X + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in memory to [64 – (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 13 and 14). mailbox registers Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port-data-transfer operation. A low-to-high transition on CLKA writes A0 – A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA and MBA is high. A low-to-high transition on CLKB writes B0 – B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and MBB is high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low. When a port’s data outputs are active, the data on the bus comes from the FIFO output register when the port mailbox-select input (MBA, MBB) is low and from the mail register when MBA/MBB is high. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB and MBB is high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA and MBA is high. The data in a mail register remains intact after it is read and changes only when new data is written to the register. parity checking The port-A inputs (A0 – A35) and port-B inputs (B0 – B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a low level on the port-parity-error flag (PEFA, PEFB). Odd- or even-parity checking can be selected and the parity-error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select input. A parity error on one or more bytes of a port is reported by a low level on the corresponding PEFA, PEFB. Port-A bytes are arranged as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each byte used as the parity bit. When odd/even parity is selected, PEFA, PEFB is low if any byte on the port has an odd/even number of low levels applied to the bits. The four parity trees used to check the A0 – A35 inputs are shared by the mail2 register when parity generation is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is selected with W/RA low, CSA low, ENA high, MBA high, and PGA high, PEFA is held high, regardless of the levels applied to the A0 – A35 inputs. Likewise, the parity trees used to check the B0 – B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from the mail1 register with parity generation is selected with W/RB low, CSB low, ENB high, MBB high, and PGB high, PEFB is held high, regardless of the levels applied to the B0 – B35 inputs. parity generation A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the SN74ABT3612 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0 – A8, A9 – A17, A18 – A26, and A27 – A35, with the most-significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0 – B8, B9 – B17, B18 – B26, and B27 – B35, with the most-significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all 36 inputs, regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the most-significant bits of each byte as the word is read to the data outputs. |
유사한 부품 번호 - SN74ABT3612PCB |
|
유사한 설명 - SN74ABT3612PCB |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |