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TLC1549M 데이터시트(PDF) 9 Page - Texas Instruments

부품명 TLC1549M
상세설명  10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
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TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS059C – DECEMBER 1992 – REVISED MARCH 1995
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
EL
Linearity error (see Note 6)
±1
LSB
EZS
Zero-scale error (see Note 7)
See Note 2
±1
LSB
EFS
Full-scale error (see Note 7)
See Note 2
±1
LSB
Total unadjusted error (see Note 8)
±1
LSB
tconv
Conversion time
See Figures 6 – 10
21
µs
tc
Total cycle time (access, sample, and conversion)
See Figures 6 – 10,
See Note 9
21
+ 10 I/O
CLOCK
periods
µs
tv
Valid time, DATA OUT remains valid after I/O CLOCK
See Figure 5
10
ns
td(I/O-DATA)
Delay time, I/O CLOCK
↓ to DATA OUT valid
See Figure 5
240
ns
tPZH, tPZL
Enable time, CS
↓ to DATA OUT (MSB driven)
See Figure 3
1.3
µs
tPHZ, tPLZ
Disable time, CS
↑ to DATA OUT (high impedance)
See Figure 3
180
ns
tr(bus)
Rise time, data bus
See Figure 5
300
ns
tf(bus)
Fall time, data bus
See Figure 5
300
ns
td(I/O-CS)
Delay time, tenth I/O CLOCK
↓ to CS↓ to abort conversion
(see Note 10)
9
µs
NOTES:
2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF – convert as all zeros (0000000000). The TLC1549 is functional with reference voltages down to 1 V (Vref + – Vref –); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A / D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the 10th I/O CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1.425
µs) after the transition.


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