TPS5615, TPS5618, TPS5625, TPS5633

SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER

SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998

5

POST OFFICE BOX 655303

detailed description (continued)

current sensing

Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the

high-side FET is on. The sampling network consists of an internal 60-

Ω switch and an external ceramic hold

capacitor. Recommended value of the hold capacitor is between 0.033

µF and 0.1 µF. The actual value should

give a time constant (60

of the sample/hold switch such that the switch does not turn on until the Vphase voltage transitions high, and

the switch turns off when the input to the high-side driver goes low. Thus sampling will occur only when the high

side FET is conducting current. The voltage on the IOUT pin equals 2 times the sensed high-side voltage. In

applications where a higher accuracy in current-sensing is required, a sense resistor can be placed in series

with the high-side FET and the voltage across the sense resistor can be sampled by the current sensing circuit.

See Figures 2 and 3.

overcurrent protection

The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent

threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage

timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against

a short-to-ground fault on the terminal common to both power FETs (Vphase).

R1

+

R2

V

S

–0.05

0.05

Figure 2. OCP Using FET ON-Resistance

Figure 3. Precision OCP Using External Resistor

R1

+

R2

V

S

–0.05

0.05

R2

2 * VS

OCP

TPS56xx

R1

IOUT

VCC

VP

CH

VS

R2

2 * VS

OCP

TPS56xx

R1

IOUT

VCC

VP

CH

VS

RS

inhibit

INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers

are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart

capacitor is released and normal converter operation begins. When the system-logic supply is connected to

INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply

exceeds the input threshold voltage of the inhibit circuit. Thus the 12-V supply and the system-logic supply

(either 5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The INHIBIT

comparator start threshold is 2.1 V and the hysteresis is 100 mV.