TSB12LV21A

(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE

SLLS273 – APRIL 1997

10

POST OFFICE BOX 655303

zoom video port switching characteristics, source clock = 30 ns with a 50% duty cycle

PARAMETER

MEASURED

TEST

CONDITION

MIN

TYP

MAX

UNIT

tsu7

Setup time, zv_hsync low, zv_vsync, zv_data_valid high before

zv_pix_clk high

1.3 V to 1.3 V

See Figure 4

12

ns

th4

Hold time, zv_hsync high, zv_vsync, zv_data_valid low after

zv_pix_clk low

1.3 V to 1.3 V

See Figure 4

14

ns

tsu8

Setup time, aux_data7–0 valid before zv_pix_clk high or low

1.3 V to 1.3 V

See Figure 4

10

ns

th5

Hold time, aux_data7–0 valid after zv_pix_clk high or low

1.3 V to 1.3 V

See Figure 4

14

ns

td11

Delay time, zv_hsync low, zv_vsync, zv_data_valid high after

zv_pix_clk low

1.3 V to 1.3 V

See Figure 5

–1

3

ns

td12

Delay time, aux_data7–0 invalid after zv_pix_clk low

1.3 V to 1.3 V

See Figure 5

–1

5

ns

tsu9

Setup time, zv_hsync low before zv_pix_clk high

1.3 V to 1.3 V

See Figure 6

25

ns

th6

Hold time, zv_hsync high after zv_pix_clk high

1.3 V to 1.3 V

See Figure 6

14

ns

tsu10 Setup time, zv_vsync high before zv_pix_clk high

1.3 V to 1.3 V

See Figure 6

10

ns

tsu11

Setup time, aux_data7–0 valid, zv_data_valid high before

zv_pix_clk high

1.3 V to 1.3 V

See Figure 6

25

ns

th7

Hold time, aux_data7–0 valid, zv_data-valid low after

zv_pix_clk high

1.3 V to 1.3 V

See Figure 6

14

ns