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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TSB12LV21BPGF 데이터시트(PDF) 10 Page - Texas Instruments |
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TSB12LV21BPGF 데이터시트(HTML) 10 Page - Texas Instruments |
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10 / 22 page  TSB12LV21B (PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER SLLS306– JULY 1998 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Serial EPROM Interface PCI Master PCI Slave Local Bus Interface Logic PCI Configuration Control and Status Registers RAM ROM AUX ZV seeprom_data seeprom_clk pci_ad31 – pci_ad0 pci_cbe3 – pci_cbe0 pci_par pci_frame pci_irdy pci_trdy pci_devsel pci_stop pci_idsel pci_perr pci_serr pci_req pci_gnt pci_clk pci_reset pci_inta 32 / 4 / PCI Bus Logic 4 / 16 / 16 / 2 / 3 / 3 / aux_clk aux_rst gpio_data3 – gpio_data0 aux_adr15 – aux_adr0 aux_data15 – aux_data0 aux_oe aux_we1 – aux_we0 aux_rdy zv_hsync, zv_vsync, zv_pix_clk aux_cs, rom_cs, ram_cs aux_int zv_data_valid DMA Engine DMA Control and Status Registers DMA Logic General Receiver FIFO Asynchronous Transmit FIFO Isosynchronous Transmit FIFO FIFO Control and Status Registers Pointer Address Mapping Logic FIFO Logic 2 / 8 / phy_ctl0 – phy_ctl1 phy_data0 – phy_data7 phy_clk50 link_cyclein phy_lreq link_cycleout 1394 LLC Control and Status Reg- isters Cycle Timer Cycle Monitor 1394 Packet Transmit Control Logic CRC Logic 1394 Packet Receive Control Logic Phy-Link Interface Logic Parallel-to-Serial Serial-to-Parallel 1394 Link Layer Control (LLC) Logic zv_ext_clk Figure 3. Functional Block Diagram |
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