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TSB12LV22 데이터시트(PDF) 11 Page - Texas Instruments |
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TSB12LV22 데이터시트(HTML) 11 Page - Texas Instruments |
11 / 45 page TSB12LV22 OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER SLLS290 – JULY 1998 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 open HCI registers base address register This register is programmed with a base address referencing the memory mapped OHCI control. When BIOS writes all ones to this register, the value read back is FFFF F800h, indicating that at least 2 Kbytes of memory address space are required for the OHCI registers. PCI register 10h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9. Bit Descriptions – Open HCI Registers Base Address Register BIT FIELD NAME ACCESS DESCRIPTION 31:11 OHCIREG_PTR rw Open HCI Register Pointer. Specifies the upper 20 bits of the 32-bit OHCI register base address. 10:4 OHCI_SZ r Open HCI Register Size. This read only field returns zeros when read, and indicates that the OHCI registers require a 2Kbyte region of memory. 3 OHCI_PF r OHCI Register Prefetch. This bit returns zero, indicating the OHCI registers are nonprefetchable. 2:1 OHCI_MEMTYPE r Open HCI Memory Type. This read only field returns zeros when read, and indicates that the base register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 OHCI_MEM r OHCI Memory Indicator. This read only bit returns zero, indicating the OHCI registers are mapped into system memory space. TI extension base address register This register is programmed with a base address referencing the memory mapped TI extension registers. Refer to the description of the OHCI Base Address Register for bit field details. PCI register 14h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCI subsystem identification register This register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM. PCI register 2Ch BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 10. Bit Descriptions – Open HCI Registers Base Address Register BIT FIELD NAME ACCESS DESCRIPTION 31:16 ru Subsystem Device ID. This field indicates the subsystem device ID. 15:0 ru Subsystem Vendor ID. This field indicates the subsystem vendor ID. |
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