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LA4815M 데이터시트(PDF) 6 Page - Sanyo Semicon Device |
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LA4815M 데이터시트(HTML) 6 Page - Sanyo Semicon Device |
6 / 14 page LA4815M No.A1373-6/14 Vbias 100k Ω + - Pre-Amp Rg2 Cin Rg1 rg OUT other IC ro LA4815M IN Cin other IC ro LA4815M Cin IN 3 3 OUT IN 3 Notes on Using the IC 1. Voltage gain settings (Pins 1 and 8) The voltage gain of the power amplifier is fixed by the internal resistors. • Pins 1 and 8 be left open : Approximately 26dB • Pins 1 and 8 connected to GND : Approximately 39.5dB Note that the voltage gain can be changed using two resistors. (See Fig. 1) • Voltage gain setting : According to the resistor connected between Pin 8 and Pin 2 (GND1) * Voltage gain = 20log (20 × (625 + Rvg1)/(125 + Rvg1)) • Output DC voltage setting : According to the resistor connected between Pin 1 and Pin 2 (GND1) * Rvg1 = Rvg2 must be satisfied. In addition, the voltage gain can also be lowered to approximately 20dB (when using 5V or 6V power supply) by an application such as shown in Fig. 2 below. • Voltage gain setting : According to the resistor connected between Pin 8 and Pin 5 (OUT) * Voltage gain = 20log (20 × (125 + Rvg3)/(10,125 + Rvg3)) • Output DC voltage setting : According to the resistor connected between Pin 1 and Pin 6 (VCC) * Set the resistor values so that the Pin 5 (OUT) DC voltage is approximately half the supply voltage. Example : When Rvg3 = 10k Ω, Rvg4 = 22kΩ (when VCC = 6V) However, note that using this method to greatly lower the voltage gain deteriorates the characteristics, so the voltage gain should be lowered only to approximately 20dB. In addition, when using a high supply voltage (7V or more), the clipped waveform may invert, so this voltage gain reduction method must not be used in these cases. Figure 1 Figure 2 2. Signal source impedance : rg The signal source impedance value rg affects the ripple rejection ratio together with input coupling capacitor Cin, so rg should be as small as possible. Therefore, when attenuating the signal at the Cin front end as shown in Fig. 4, the constants should be set in consideration of these characteristics. Using the smallest resistor Rg1 value possible is recommended. In addition, when setting the signal level, the voltage gain should be set on the LA4815M side and the input front-end should be configured using only the input coupling capacitor, Cin, as shown in Fig. 5 in order to maximize the ripple rejection ratio. Figure 4 Figure 3 Figure 5 LA4815M Rvg1 Rvg2 GAIN2 GAIN1 GND1 VCC OUT LA4815M Rvg3 Rvg4 GAIN2 GAIN1 GND1 VCC OUT 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 |
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