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STA2065A 데이터시트(PDF) 9 Page - STMicroelectronics |
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STA2065A 데이터시트(HTML) 9 Page - STMicroelectronics |
9 / 20 page STA2065 System description Doc ID16050 Rev 1 9/20 2.6 Communication interfaces 2.6.1 USB STA2065 embeds two USB2.0 OTG high-speed interfaces named USB0 and USB1, featuring: a) High-speed signalling rate at 480 Mbit/s b) Support for full-speed (12 Mbit/s) signaling bit rate c) Support for session request protocol (SRP) and host negotiation protocol (HNP) d) Up to 7 bidirectional endpoints plus control endpoint 0 e) 8192 bytes maximum FIFO dimension f) Dynamic FIFO allocation To reduce total system cost, USB0 is equipped with a built-in USB 2.0 HIGH-SPEED / OTG PHY, while USB1 is provided with both an USB 2.0 FULL-SPEED PHY and a standard ULPI interface able to connect to an external SDR/DDR PHY. With the goal of reducing the BOM cost for the customer, the USB 2.0 PHY also supports this additional muxing scheme: ● the USB D- wire is used as either the USB D- signal or UART receive data signal ● the USB D+ wire is used as either the USB D+ signal or the UART transmit data signal 2.6.2 UART STA2065 features four Autobaud UARTs. One offers all modem control/status signals. They are enhanced version of the industry-standard 16C550 UART. 2.6.3 I2C The I2C controller is an interface designed to support the physical and data link layer according to I2C standard revision 2.1 (January 2000). The I2C bus is a 2-wire serial bus that provides a low-cost interconnection between ICs. STA2065 features three I2C interfaces. 2.6.4 MSP The multichannel serial port (MSP) is a synchronous receive and transmit serial interface. STA2065 features four MSPs. 2.6.5 SSP STA2065 features two SSPs up to 24Mbit/sec for synchronous serial communication with external peripherals. SPI, MicroWire, T.I. and mono-directional protocols are supported with programmable word length up to 32 bits. 2.6.6 SPDIF This interface takes SPDIF as input and extracts data and other channel information encrypted in SPDIF Frame format as per IEC958 standards. Data can be transferred to memory, using DMA support, or directly to C3 decoder without CPU intervent. SPDIF block supports up to 2X data streams. |
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