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ISL3034E 데이터시트(PDF) 9 Page - Intersil Corporation |
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ISL3034E 데이터시트(HTML) 9 Page - Intersil Corporation |
9 / 16 page 9 FN6492.0 March 31, 2009 applications). The low static pull-up current is easily overdriven by an active pull-down, and the feedback nature of the accelerators (i.e., the accelerator firing in one direction also triggers the accelerator in the opposite direction) aids the passive pull-up once the input signal passes the accelerator’s high threshold. The pull-up current and load capacitance set the input signal rise time, and thus the maximum data rate. For slow data rates the internal pull-up current may suffice, but higher data rates - or more heavily loaded signal lines - may require an external pull-up resistor. Using External Bus Resistors As mentioned earlier, these level translators incorporate I/O pin pull-up current sources when enabled, and I/O pin pull-up resistors in SHDN (except for the ISL3035E’s I/OVCC pins). Therefore, external pull-up or pull-down resistors shouldn’t be necessary, and aren’t recommended, unless using high-speed open drain signaling. Power Supplies WIDE SUPPLY RANGE These ICs operate from a wide range of supply voltages. VL is designed to connect to the supply of 1.5V, 1.8V, and 2.5V powered devices, while VCC is targeted for 2.5V, and 3.3V components. Remember that VCC must be greater than VL for proper operation. POWER SUPPLY SEQUENCING Either VCC or VL may be powered up first, but the IC remains in SHDN until VCC exceeds VL by as much as 200mV. VL may exceed VCC by as much as 4V without causing any damage. I/O PIN INPUT THRESHOLDS VS SUPPLY VOLTAGE Even though the “Electrical Specification” table on page 4 shows the I/O pin input thresholds (VIH, VIL) with a fixed delta from the supplies or GND, the thresholds are better represented as a percentage of the supplies. The typical I/OVCC and CLK_VCC VIH runs about 55% to 60% of VCC, while the corresponding VIL runs about 33% of VCC. The typical I/OVL and CLK_VL VIH runs about 60% to 70% of VL, while the corresponding VIL runs about 25% to 35% of VL. Low Power SHDN Mode This family of level translators features a low power SHDN mode that tri-states all the I/O and output pins, considerably reduces current consumption, and enables any pull-up resistors on a port’s I/O pins (see Table 1). The ISL3034E and ISL3036E enter the SHDN mode when the EN input switches low, or automatically when the VCC voltage drops below the VL voltage. The ISL3035 has no enable pin, so it enters SHDN only if VCC drops below VL. The VL supply powers the EN circuitry. ISL3034E and ISL3036E The ISL3034E and ISL3036E are general purpose level translators featuring an enable pin, and six or four channels, respectively. Both products include SHDN mode 16.5k Ω pull-ups on the I/OVCC and I/OVL pins. ISL3035E The ISL3035E specifically targets memory card applications, and Figure 6 illustrates its use in an SD Card application. Instead of six general purpose channels, the ISL3035E features five general purpose channels and one dedicated CLK channel. In memory card applications, the CLK channel is a unidirectional signal driven by the host controller and used by the memory card to synchronize data reads and writes. The ISL3035E’s CLK channel is unique in that the host CLK applied to the CLK_VL pin routes to the memory card via the CLK_VCC pin, but it also loops back to the host on the CLK_RET pin. This CLK_RET signal better mimics the timing of “read” data returned from the memory card (see Figure 21 for signal timing), so using CLK_RET as the host’s input CLK improves the CLK to data timing relationship. CLK_RET is strictly an output, and CLK_VL is strictly an input. If an ISL3035E application needs a sixth I/O channel then the user needs to connect CLK_VL and CLK_RET together. Connected this way, the combination channel has the same architecture as the other I/O channels. Both CLK_RET and CLK_VL have equivalent pull-up current sources and SHDN pull-up resistors, so connecting these two pins together doubles the pull-up current in either mode. The bit-by-bit auto direction control eliminates the need for GPIO signals to control the flow of data on the CMD and DAT lines. The ISL3035E has no enable pin, so it only enters the low power SHDN mode when VCC drops below VL. There are no SHDN pull-up resistors on the I/OVCC and CLK_VCC pins, but there are 75k Ω pull-ups on the I/OV L, CLK_VL, and CLK_RET pins. FIGURE 6. ISL3035E IN AN SD CARD APPLICATION VL VCC I/OVL_ I/OVL_ ISL3035E CLK_RET I/OVL_ I/OVL_ I/OVL_ GND I/OVCC_ I/OVCC_ I/OVCC_ I/OVCC_ I/OVCC_ CLK_VL CLK_VCC DAT3 DAT2 DAT1 DAT0 CMD CLOCK GND GND +3.3V SD CARD DAT3 DAT2 CLOCK_IN DAT1 DAT0 CMD CLOCK +1.8V SYSTEM CONTROLLER 0.1 µF 0.1 µF +1.8V 1 µF +3.3V HOST 1 µF ISL3034E, ISL3035E, ISL3036E |
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