8

FN6580.1

March 5, 2009

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 1A. MEASUREMENT POINTS

capacitance.

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

FIGURE 3. OFF-ISOLATION TEST CIRCUIT

50%

90%

V+

0V

0V

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

V

OUT

V

(NO or NC)

R

L

R

L

r

ON

+

------------------------

=

SWITCH

INPUT

LOGIC

INPUT

COM

NO OR NC

IN

50

Ω

35pF

GND

V+

C

ON

OFF

ON

Q =

SWITCH

OUTPUT

LOGIC

INPUT

V+

0V

GND

COM

NO OR NC

V+

C

LOGIC

INPUT

IN

Repeat test for all switches.

ANALYZER

SIGNAL

GENERATOR

V+

C

0V OR V+

NO OR NC

COM

IN

GND

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

*50

Ω SOURCE

V+

C

0V OR V+

NO OR NC

COM

IN

GND

100mA

Repeat test for all switches.

ISL54060, ISL54061