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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ISL12082IUZ 데이터시트(PDF) 5 Page - Intersil Corporation |
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ISL12082IUZ 데이터시트(HTML) 5 Page - Intersil Corporation |
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5 / 26 page  5 FN6731.3 November 24, 2008 Cpin SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz, VDD = 5V, VIN =0V, VOUT = 0V 10 pF 7, 8 fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window 900 ns tBUF Time the Bus Must Be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window 0 900 ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD 600 ns tHD:STO STOP Condition Hold Time From SDA rising edge to SCL falling edge Both crossing 70% of VDD 600 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window 0ns tR SDA and SCL Rise Time From 30% to 70% of VDD 20 + 0.1 x Cb 300 ns 7, 8 tF SDA and SCL Fall Time From 70% to 30% of VDD 20 + 0.1 x Cb 300 ns 7, 8 Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 7, 8 Rpu SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k Ω to ~2.5kΩ For Cb = 40pF, max is about 15k Ω to ~20kΩ 1k Ω 7, 8 NOTES: 2. IRQ and fOUT Inactive. 3. LPMODE = 0 (default). 4. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 5. Typical values are for T = +25°C and 3.3V supply voltage. 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits should be considered typical and are not production tested. 8. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 9. Parameters are for 10 Ld MSOP package only. Serial Interface Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 5) MAX (Note 6) UNITS NOTES ISL12082 |
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