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BU2050F 데이터시트(PDF) 9 Page - Rohm |
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BU2050F 데이터시트(HTML) 9 Page - Rohm |
9 / 25 page BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS Technical Note 9/24 www.rohm.com 2009.06 - Rev.A © 2009 ROHM Co., Ltd. All rights reserved. 【 BU2092F/BU2092FV】 ● Pin descriptions ● Timing chart Fig. 4 1. After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into the DATA terminal. 2. Qx parallel output data of the shift register is set after the 12 th clock by the LCK. 3. Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK. 4. Data retained in the internal latch circuit is output when the OE is in the “L” section. [ Truth Table] Input Function CLOCK DATA LCK OE × × × H Output (Q0~Q11) Disable × × × L Output (Q0~Q11) Enable L × × Store “L” in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) H × × Store “H” in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) × × × The data of shift register has no change. × × × The data of shift register is transferred to the storage register. × × × The data of storage register has no change. Pin No. Pin Name I/O Function 1 VSS - GND 2 DATA I Serial Data Input 3 CLOCK I Shift clock of DATA (Rising Edge Trigger) 4 LCK I Latch clock of DATA (Rising Edge Trigger) 5~11, 14~18 Q0~Q11 O Parallel Data Output (Nch Open Drain FET) Latch Data L H Output FET ON OFF 12, 13 N.C. - Non connected 17 OE I Output Enable (“H” level : output FET is OFF) 18 VDD - Power Supply CLOCK LCK DATA DATA11 DATA10 DATA9 DATA1 DATA0 OE Qx Previous DATA DATA11~0 “H” Note) Diagram shows a status where a pull-up resistor is connected to output. |
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