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CS4353-CNZ 데이터시트(PDF) 11 Page - Cirrus Logic

부품명 CS4353-CNZ
상세설명  3.3 V Stereo Audio DAC with 2 VRMS Line Output
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

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DS803F1
11
CS4353
DC ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise specified): VCP = VA = VL = 3.3 V; AGND = DGND = CPGND = 0 V; SDIN = 0;
all voltages with respect to ground.
Notes: 15. Current consumption increases with increasing sample rate and increasing MCLK frequency. Typical
values are based on Fs = 48 kHz and MCLK = 12.288 MHz. Maximum values are based on highest
sample rate and highest MCLK frequency; see Switching Specifications - Serial Audio Interface. Vari-
ance between speed modes is small.
16. Power-down is defined as RESET pin = Low with all clock and data lines held static low. All digital inputs
have a weak pull-down (approximately 50 k
Ω) which is only present during reset. Opposing this pull-
down will slightly increase the power-down current.
17. Valid with the recommended capacitor value on VBIAS as shown in the typical connection diagram in
Section 3.
18. Typical voltage shown for “Initialization State”, see Section 4.8. Typical voltage may be up to 1.5 V lower
during normal operation.
2.1
Digital I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in Table 1. Logic levels should not
exceed the corresponding power supply voltage.
Table 1. Digital I/O Pin Characteristics
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current (Note 15)
Normal Operation
Power-Down, All Supplies (Note 16)
IVCP
IVA
IVL
IPD
-
-
-
-
36
2.4
0.1
65
43
3
0.2
-
mA
mA
mA
μA
Power Dissipation (All Supplies)
Normal Operation, 1_2VRMS = 0
(Note 15)
Power-Down (Note 16)
-
-
127
1
152
-
mW
mW
Power Supply Rejection Ratio (Note 17)
(1 kHz)
(60 Hz)
PSRR
-
-
60
60
-
-
dB
dB
DC Output Voltages
Pin Voltage
FLYP+ to FLYP-
VFILT+ to GND (Note 18)
FLYN+ to FLYN-
GND to VFILT- (Note 18)
VA to VBIAS
-
-
-
-
-
3.3
6.6
6.6
6.6
2.1
-
-
-
-
-
V
V
V
V
V
Pin Name
Power Supply
I/O
Driver
Receiver
RESET
VL
Input
-
0.9 V - 3.3 V, with Hysteresis
MCLK
Input
-
0.9 V - 3.3 V
LRCK
Input
-
0.9 V - 3.3 V
SCLK
Input
-
0.9 V - 3.3 V
SDIN
Input
-
0.9 V - 3.3 V
DEM
Input
-
0.9 V - 3.3 V
I²S/LJ
Input
-
0.9 V - 3.3 V
1_2VRMS
Input
-
0.9 V - 3.3 V


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