전자부품 데이터시트 검색엔진 |
|
FDG410NZ 데이터시트(PDF) 4 Page - Fairchild Semiconductor |
|
FDG410NZ 데이터시트(HTML) 4 Page - Fairchild Semiconductor |
4 / 7 page www.fairchildsemi.com 4 ©2009 Fairchild Semiconductor Corporation FDG410NZ Rev.B Figure 7. 01 23 4 5 6 0 1 2 3 4 5 Qg, GATE CHARGE (nC) ID = 2.2 A VDD = 10 V VDD = 5 V VDD = 15 V Gate Charge Characteristics Figure 8. 0.1 1 10 20 10 100 1000 f = 1 MHz VGS = 0 V VDS, DRAIN TO SOURCE VOLTAGE (V) Crss Coss Ciss Capacitance vs Drain to Source Voltage Figure 9. Forward Bias Safe Operating Area 0.01 0.1 1 10 100 0.01 0.1 1 10 10 s 0.1 ms 10 ms DC 1 s 100 ms 1 ms VDS, DRAIN to SOURCE VOLTAGE (V) THIS AREA IS LIMITED BY r DS(on) SINGLE PULSE TJ = MAX RATED RθJA = 333 oC/W TA = 25 oC Figure 10. 02 46 8 10 12 14 10 -5 10 -3 10 -1 10 1 10 3 10 5 VGS = 0 V TJ = 25 oC TJ = 125 oC VGS, GATE TO SOURCE VOLTAGE (V) Gate Leakage Current vs Gate to Source Voltage Figure 11. Single Pulse Maximum Power Dissipation 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 V GS = 4.5 V t, PULSE WIDTH (sec) SINGLE PULSE RθJA = 333 oC/W TA = 25 oC Typical Characteristics T J = 25 °C unless otherwise noted |
유사한 부품 번호 - FDG410NZ |
|
유사한 설명 - FDG410NZ |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |