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SMM153 데이터시트(PDF) 4 Page - Summit Microelectronics, Inc.

부품명 SMM153
상세설명  10-bit Digital Differential Voltage and Current Monitor
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제조업체  SUMMIT [Summit Microelectronics, Inc.]
홈페이지  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMM153 데이터시트(HTML) 4 Page - Summit Microelectronics, Inc.

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SMM153
Preliminary Information
Summit Microelectronics, Inc
2.0 8/12/2008
4
Pin
Number
Pin
Type
Pin Name
Pin Description
28
I/O
SDA
I
2C Bi-directional data line
1
I
SCL
I
2C clock input.
2
I
A2
4
I
A1
6
I
A0
The address pins are biased either to VDD, GND or left floating. This
allows for a total of 21 distinct device addresses. When communicating with
the SMM153 over the 2-wire bus these pins provide a mechanism for
assigning a unique bus address.
3, 9, 22, 27
I/O
GPIO0,1,2,3
General purpose inputs/outputs.
8
I
WP
Programmable Write Protect active high/low input. When asserted, writes
to the configuration registers and general purpose EE are not allowed. The
WP input is internally tied to VDD with a 50K
Ω resistor.
10, 13
CAP
CAPM+, -
External capacitor inputs used to filter the VM+/VM- inputs, 0.22
µF.
14
I
VM+
Voltage monitor input. Connect to the DC-DC converter positive sense line
or it’s +Vout pin.
15
I
VM-
Voltage monitor input. Connect to the DC-DC converter negative sense line
or it’s -Vout pin.
18
I
CS+
Current monitor input + side. Connect to the input supply side of the current
sense resistor.
17
I
CS-
Current monitor input - side. Connect to the load side of the current sense
resistor.
26
PWR
VREF
Internal reference voltage of 1.25V. Connect to GND through a 0.1uF
capacitor to improve noise immunity.
16
O
CAPC
External capacitor input used to filter the CS+/CS- input. Typical value: 1uF.
21
PWR
VDD
Power supply of the part.
23
PWR
VDD_CAP
External capacitor input used to filter the internal VDD supply rail.
5, 7
GND
GND
Ground of the part. The SMM153 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
19
I
COMP1
12
I
COMP2
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the internally programmable VREF
voltage. Each comparator can be independently programmed to monitor for
UV or OV. The monitor level is set externally with a resistive voltage
divider.
11
O
FAULT#
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
29
GND
GND
GND. The bottom side metal plate (Pad 29) should be connected on the
PCB for optimized noise performance.
PIN DESCRIPTION


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