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CS8427-CSZ 데이터시트(PDF) 8 Page - Cirrus Logic

부품명 CS8427-CSZ
상세설명  96 kHz Digital Audio Interface Transceiver
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8427-CSZ 데이터시트(HTML) 8 Page - Cirrus Logic

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CS8427
8
DS477F4
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Notes: 8. The active edges of ISCLK and OSCLK are programmable.
9. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising
edge. When these signals are derived from RMCK, they are clocked from its falling edge.
10. The polarity of ILRCK and OLRCK is programmable.
11. No more than 128 SCLK per frame.
12. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
13. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has
changed.
Parameter
Symbol
Min
Typ
Max
Units
OSCLK Active Edge to SDOUT Output Valid
(Note 8)
tdpd
-
-
20
ns
SDIN Setup Time Before ISCLK Active Edge
(Note 8)
tds
20
-
-
ns
SDIN Hold Time After ISCLK Active Edge
(Note 8)
tdh
20
-
-
ns
Master Mode
O/RMCK to I/OSCLK active edge delay
(Note 8, 9)
tsmd
0
-
10
ns
O/RMCK to I/OLRCK delay
(Note 10)
tlmd
0
-
10
ns
I/OSCLK and I/OLRCK Duty Cycle
-
50
-
%
Slave Mode
I/OSCLK Period
(Note 11)
tsckw
36
-
-
ns
I/OSCLK Input Low Width
tsckl
14
-
-
ns
I/OSCLK Input High Width
tsckh
14
-
-
ns
I/OSCLK Active Edge to I/OLRCK Edge
(Note 8, 10, 12)
tlrckd
20
-
-
ns
I/OLRCK Edge Setup Before I/OSCLK Active Edge
(Note 8, 10, 13)
tlrcks
20
-
-
ns
sckh
sckl
sckw
t
t
t
tdpd
SDOUT
(input)
(input)
SDIN
dh
t
ds
t
lrcks
t
lrckd
t
ISCLK
OSCLK
ILRCK
OLRCK
t
sm d
t
lm d
Ha rd wa re M o d e
So ftw a re M o d e
IS C L K
OS C L K
(o utpu t)
IL RCK
O L RCK
(o utpu t)
RM C K
(o utpu t)
RM C K
(o utpu t)
OM C K
(inp ut)
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing


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