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STM32F103RBH7TR ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 89 Page - STMicroelectronics

๋ถ€ํ’ˆ๋ช… STM32F103RBH7TR
์ƒ์„ธ๋‚ด์šฉ  Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
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STM32F103RBH7TR ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 89 Page - STMicroelectronics

 
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STM32F103x8, STM32F103xB
Revision history
Doc ID 13587 Rev 11
89/92
14-Mar-2008
5
Figure 2: Clock tree on page 20 added.
Maximum TJ value given in Table 8: Thermal characteristics on
page 35.
CRC feature added (see CRC (cyclic redundancy check) calculation
unit on page 9 and Figure 9: Memory map on page 31 for address).
IDD modified in Table 16: Typical and maximum current consumptions in
Stop and Standby modes.
ACCHSI modified in Table 24: HSI oscillator characteristics on page 52,
note 2 removed.
PD, TA and TJ added, tprog values modified and tprog description clarified
in Table 28: Flash memory characteristics on page 53.
tRET modified in Table 29: Flash memory endurance and data retention.
VNF(NRST) unit corrected in Table 37: NRST pin characteristics on
page 60.
Table 41: SPI characteristics on page 64 modified.
IVREF added to Table 45: ADC characteristics on page 68.
Table 47: ADC accuracy - limited test conditions added. Table 48: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
characteristics on page 73).
Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36
footprints added (see Figure 40, Figure 42, Figure 46 and Figure 36).
Section 6.2: Thermal characteristics on page 82 modified,
Section 6.2.1 and Section 6.2.2 added.
Appendix A: Important notes on page 81 removed.
21-Mar-2008
6
Small text changes. Figure 9: Memory map clarified.
In Table 29: Flash memory endurance and data retention:
โ€“NEND tested over the whole temperature range
โ€“ cycling conditions specified for tRET
โ€“tRET min modified at TA = 55 ยฐC
V25, Avg_Slope and TL modified in Table 49: TS characteristics.
CRC feature removed.
22-May-2008
7
CRC feature added back. Small text changes. Section 1: Introduction
modified. Section 2.2: Full compatibility throughout the family added.
IDD at TA max = 105 ยฐC added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes on page 42.
IDD_VBAT removed from Table 21: Typical current consumption in
Standby mode on page 47.
Values added to Table 40: SCL frequency (fPCLK1= 36 MHz.,VDD =
3.3 V) on page 63.
Figure 27: SPI timing diagram - slave mode and CPHA = 0 on page 65
modified. Equation 1 corrected.
tRET at TA = 105 ยฐC modified in Table 29: Flash memory endurance and
data retention on page 54.
VUSB added to Table 43: USB DC electrical characteristics on page 67.
Figure 47: LQFP100 PD max vs. TA on page 84 modified.
Axx option added to Table 57: Ordering information scheme on
page 85.
Table 58.
Document revision history (continued)
Date
Revision
Changes


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