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SA08 데이터시트(PDF) 4 Page - Cirrus Logic |
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SA08 데이터시트(HTML) 4 Page - Cirrus Logic |
4 / 5 page P r o d u c t I n n o v a t i o n F r o m SA08 4 SA08U adjusted so as to reduce the switch- ing noise well below 100 mV to prevent false current limit- ing. The sum of the DC level plus the noise peak will de- termine the current limiting value. As in most switching circuits it may be difficult to deter- mine the true noise amplitude without careful attention to grounding of the oscilloscope probe. Use the shortest possible ground lead for the probe and connect exactly at the GND terminal of the amplifier. Suggested starting values are C FILTER = .1uF, R FILTER = 5k . The required value of R LIMIT in voltage mode may be cal- culated by: R LIMIT = .1 V / ILIMIT where R LIMIT is the required resistor value, and ILIMIT is the maximum desired current. In current mode the required value of each R LIMIT is 2 times this value since the sense voltage is divided down by 2 (see Figure B). If R SHDN is used it will further divide down the sense voltage.The shutdown divider network will also have an effect on the filtering circuit. BYPASSING Adequate bypassing of the power supplies is required for proper operation. Failure to do so can cause erratic and low efficiency operation as well as excessive ringing at the out- puts. The Vs supply should be bypassed with at least a 1µF ceramic capacitor in parallel with another low ESR capacitor of at least 10µF per amp of output current. Capacitor types rated for switching applications are the only types that should be considered. The bypass capacitors must be physically connected directly to the power supply pins. Even one inch of lead length will cause excessive ringing at the outputs. This is due to the very fast switching times and the inductance of the lead connection. The bypassing requirements of the Vcc supply are less stringent, but still necessary. A .1µF to .47µF ceramic capacitor connected directly to the Vcc pin will suffice. STARTUPCONDITIONS The high side of the IGBT output bridge circuit is driven by bootstrap circuit and charge pump arrangement. In order for the circuit to produce a 100% duty cycle indefinitely the low side of each half bridge circuit must have previously been in the ON condition. This means, in turn, that if the input signal to the SA08 at startup is demanding a 100% duty cycle, the output may not follow the command and may be in a tri-state condition. The ramp signal must cross the input signal at some point to correctly determine the output state. After the ramp crosses the input signal level one time, the output state will be correct thereafter. GENERAL Please read Application Note 30 on "PWM Basics". Refer to Application Note 1 "General Operating Considerations" for helpful information regarding power supplies, heat sinking and mounting. Visit www.Cirrus.com for design tools that help automate pwm filter design;heat sink selection;Apex Precision Power’s completeApplication Notes library;Technical Seminar Workbook; and Evaluation Kits. CLOCKCIRCUITANDRAMPGENERATOR The clock frequency is internally set to a frequency of ap- proximately 45kHz. The CLK OUT pin will normally be tied to the CLK IN pin. The clock is divided by two and applied to an RC network which produces a ramp signal. An external clock signal can be applied to the CLK IN pin for synchronization purposes, but must be 45 kHz +/- 2%. FLAGOUTPUT Whenever the SA08 has detected a fault condition, the flag output is set high (10V). When the programmable low side current limit is exceeded, the FLAG output will be set high. The FLAG output will be reset low on the next clock cycle.This reflects the pulse-by-pulse current limiting feature. When the internally-set high side current limit is tripped or the thermal limit is reached, the FLAG output is latched high. See PRO- TECTION CIRCUITS below. PROTECTIONCIRCUITS A fixed internal current limit senses the high side current. Should either of the outputs be shorted to ground the high side current limit will latch off the output transistors.The temperature of the output transistors is also monitored.Should a fault condi- tion raise the temperature of the output transistors to 165°C the thermal protection circuit latch off the output transistors. The latched condition can be cleared by either recycling the V cc power or by toggling the I LIMIT/SHDN input with a 10V pulse. See Figures A and B.The outputs will remain off as long as the shutdown pulse is high (10V). CURRENTLIMIT There are two load current sensing pins, I SENSE A and I SENSE B. The two pins can be shorted in the voltage mode connection but both must be used in the current mode connec- tion (see figuresA and B).It is recommended that R LIMIT resistors be non-inductive. Load current flows in the I SENSE pins. To avoid errors due to lead lengths connect the I LIMIT/SHDN pin directly to the R LIMIT resistors (through the filter network and shutdown divider resis- tor) and connect the R LIMIT resistors directly to the GND pin. Switching noise spikes will invariably befoundattheISENSE pins. The noise spikes could trip the current limit threshold which is only 100 mV. R FILTER and C FILTER should be I SENSE A I SENSE B I LIMIT/SHDN R FILTER C FILTER R LIMIT 1N4148 SHUTDOWN SIGNAL 5K FIGURE A. CURRENT LIMIT WITH SHUTDOWN VOLTAGE MODE. 0/10V I SENSE A I SENSE B I LIMIT/SHDN R FILTER C FILTER 1N4148 0/10V SHUTDOWN SIGNAL 5K 5K FIGURE B. CURRENT LIMIT WITH SHUTDOWN CURRENT MODE. R LIMIT R LIMIT |
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