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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADP1043AACPZ-RL 데이터시트(PDF) 46 Page - Analog Devices |
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ADP1043AACPZ-RL 데이터시트(HTML) 46 Page - Analog Devices |
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46 / 72 page  ADP1043A Rev. 0 | Page 46 of 72 Table 44. Register 0x30—OrFET Bits Name R/W Description [7:6] Accurate OrFET threshold R/W These bits program the voltage difference between CS2+ and CS2− at which the accurate OrFET flag is set. The CS2+ and CS2− input pins are used to control this function. Bit 7 Bit 6 Voltage Drop Across Sense Resistor from CS2+ to CS2− (Threshold) 0 0 0 mV 0 1 Reserved 1 0 Reserved 1 1 Reserved [5:4] OrFET enable threshold R/W These bits program the voltage difference between VS1 and VS2 before the OrFET is enabled. The VS1 and VS2 input pins are used to control the OrFET enable function. Bit 5 Bit 4 Voltage Difference from VS1 to VS2 % of ADC Full Range 12 V VOUT (mV) 48 V VOUT (mV) 0 0 −0.5 −93 −372 0 1 0 0 0 1 0 1 186 744 1 1 2 372 1488 [3:2] Fast OrFET threshold R/W These bits program the threshold voltage difference between CS2+ and CS2− at which the OrFET is disabled. The CS2+ and CS2− input pins are used to control this function. The internal circuit is an analog comparator. Bit 3 Bit 2 Voltage Difference from CS2+ to CS2− (mV) 0 0 −100 0 1 −75 1 0 −50 1 1 −25 1 Fast OrFET debounce R/W These bits determine the debounce on the fast OrFET control before it disables the OrFET. 0 = 40 ns. 1 = 200 ns. 0 Fast OrFET bypass R/W Set this bit to completely bypass the fast OrFET control. To also bypass the accurate OrFET disable control, the response to the accurate OrFET disable flag should be set to ignore. VOLTAGE SENSE REGISTERS Table 45. Register 0x31—VS3 Voltage Setting (Remote Voltage) Bits Name R/W Description [7:0] VS3 voltage setting R/W This register is used to set the output voltage (voltage differential at the VS3+ and VS3− pins). Programmable from 0% to 155% of nominal voltage. Each LSB corresponds to a 0.6% increase. Setting this register to a value of 0xA5 gives an output voltage setting of 100% of the nominal voltage. This is the default value and is stored in this register when shipped from the factory. Updating the VS3 voltage setting is a two-stage process. First, the user must change the value in this register; this information is stored in a shadow register. To latch the new VS3 voltage setting into the state machine, the user must set the GO bit (Register 0x5D[0]). Table 46. Register 0x32—VS1 Overvoltage Limit (OVP) Bits Name R/W Description [7:3] VS1 OVP setting R/W Local overvoltage limit. This limit is programmable from 107.7% to 145.3% of the nominal VS1 voltage; 0x00 corresponds to 107.7%. Each LSB results in an increase of 1.21%. The VS1 OVP threshold is calculated as follows: VS1_OVP_Threshold = [(89 + VS1_OVP_Setting)/128] × 1.55 V For example, if the VS1 OVP setting is 10, then VS1_OVP_Threshold = [(89 + 10)/128] × 1.55 V = 1.2 V Setting these bits to 0 gives an OVP limit of 107.7% of the nominal VS1 voltage. Setting these bits to 10 gives an OVP limit of 120% of the nominal VS1 voltage. Setting these bits to 20 gives an OVP limit of 132% of the nominal VS1 voltage. Setting these bits to 31 gives an OVP limit of 145.3% of the nominal VS1 voltage. 2 Reserved R/W Reserved. |
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